Linda Sun

US Patent:

8300532, Oct 30, 2012

Filed:

Sep 23, 2008

Appl. No.:

12/235677

Inventors:

Anjan Venkatramani - Los Altos CA, US
Kannan Varadhan - San Jose CA, US
Jean-Marc Frailong - Los Altos CA, US
Sanjay Gupta - Santa Clara CA, US
Linda Sun - San Jose CA, US
Sankar Ramamoorthi - San Jose CA, US
Pradeep Sindhu - Los Altos Hills CA, US
Anand S. Athreya - San Jose CA, US
Chih-Wei Chao - Saratoga CA, US
Shuhua Ge - Fremont CA, US

Assignee:

Juniper Networks, Inc. - Sunnyvale CA

International Classification:

H04L 12/26
H04L 12/56

US Classification:

370235, 370392

Abstract:

A method may include receiving a packet at an ingress line interface in a forwarding plane of a network element, the packet including header information. The method may also include conducting a flow table lookup in the forwarding plane to identify an existing flow for the packet and determining, in the forwarding plane and based on the header information, whether a predicted flow can be identified for the packet if an existing flow can not be identified. The method may further include performing a service access control list (ACL) lookup in the forwarding plane if a predicted flow can not be identified; and forwarding the packet to one of a services plane or an egress line interface in the forwarding plane based on one of the existing flow, the predicted flow, or the service ACL lookup.

US Patent:

20130154677, Jun 20, 2013

Filed:

Dec 20, 2011

Appl. No.:

13/332285

Inventors:

Linda K. Sun - Fremont CA, US
Harry Muljono - San Ramon CA, US

International Classification:

G01R 31/3187

US Classification:

3247503

Abstract:

A pad capacitance test circuit may be coupled to one or more pads of an electronic circuit, such as a processor. The pad capacitance test circuit may be located on a die including the electronic circuit. The pad capacitance test circuit may reset a pad voltage of one or more of the pads to zero, and then couple the pad to a supply voltage through a pullup resistor for a time period. The final pad voltage at or near the end of the period of time may be measured. The pad capacitance may be determined from the measured value of the final pad voltage and known values of the supply voltage, the time period, and resistance of the pullup resistor.

US Patent:

20190305549, Oct 3, 2019

Filed:

Mar 29, 2018

Appl. No.:

15/939807

Inventors:

Harry Muljono - Union City CA, US
Horaira Abu - Fremont CA, US
Linda K. Sun - Fremont CA, US

International Classification:

H02H 9/04

Abstract:

Some embodiments include apparatuses having an electrostatic discharge (ESD) protection circuit coupled to a node, and first, second, and third circuits coupled to the node. The first circuit includes a first charge pump to cause a voltage at the node during activation of the first circuit to change from a first voltage value to a second voltage value within first multiple periods of a clock signal, the second voltage value being less than the first voltage value. The second includes a second charge pump to cause a voltage at the node during activation of the second circuit to change from a third voltage value to a fourth voltage value during second multiple periods of the clock signal, the fourth voltage value being greater than the third voltage value. The third circuit generates information based on the values of the voltage at the node during activation of the first and second circuits. The apparatuses optionally include a fourth circuit to generate an additional voltage at an additional node. The additional voltage has a negative voltage value. The additional node is coupled to a gate of at least one transistor of the first circuit.

US Patent:

20190280691, Sep 12, 2019

Filed:

May 20, 2019

Appl. No.:

16/417511

Inventors:

- Santa Clara CA, US
Linda K. Sun - Fremont CA, US
Maria Jose Garcia Garcia de Leon - Zapopan, MX
Raul Enriquez Shibayama - Zapopan, MX
Abraham Isidoro Munoz - Zapopan, MX
Carlos Eduardo Lozoya Lopez - Tlajomulco de Zuniga, MX

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03K 19/00
H03K 19/0175
H04L 25/02
G06F 13/40

Abstract:

An apparatus includes a terminal, a first device coupled to the terminal via a first node, the first device to drive a signal on the terminal via the first node, and a second device coupled to the terminal via a second node, wherein the second device comprises a dynamic on-die termination (ODT) circuit coupled to the second node. The dynamic ODT circuit includes: a bus holder circuit to receive the signal from the first device at the second node and select a termination voltage based on the signal, a response delay circuit coupled to the bus holder circuit, the response delay circuit to delay application of the termination voltage to the second node, and a time blanking delay circuit coupled to the bus holder circuit and the response delay circuit to prevent the termination voltage from changing before a threshold period of time elapses.