Loreto Y Cantillep
age ~61
from San Jose, CA
- Also known as:
-
- Loret Cantillep
- Loreto Cancillep
- Phone and address:
-
247 Capitol Ave, San Jose, CA 95127
(408)2586720
Loreto Cantillep Phones & Addresses
- 247 Capitol Ave, San Jose, CA 95127 • (408)2586720
- 422 10Th St, San Jose, CA 95112
- 8041 Shay Cir, Stockton, CA 95212 • (209)9521997
- Santa Clara, CA
Resumes
Senior Manufacturing Engineer
view sourceLocation:
1380 Willow Rd, Menlo Park, CA 94025
Industry:
Semiconductors
Work:
Pacific Biosciences
Senior Manufacturing Engineer
Pacific Biosciences
Staff Manufacturing Engineer
Vertical Circuits 2007 - 2009
Senior Process Development Engineer and Tpm
Stats Chippac Aug 2005 - Sep 2007
Technical Program Manager
Corwil Technologies Ltd. 2003 - 2005
Process Development Engineer
Senior Manufacturing Engineer
Pacific Biosciences
Staff Manufacturing Engineer
Vertical Circuits 2007 - 2009
Senior Process Development Engineer and Tpm
Stats Chippac Aug 2005 - Sep 2007
Technical Program Manager
Corwil Technologies Ltd. 2003 - 2005
Process Development Engineer
Education:
University of Cebu 1986 - 1991
Bachelor of Science In Mechanical Engineering, Bachelors, Engineering State College of Science and Technology 1979 - 1981
University of Cebu 1979 - 1981
Bachelor of Science In Mechanical Engineering, Bachelors, Engineering State College of Science and Technology 1979 - 1981
University of Cebu 1979 - 1981
Skills:
Design of Experiments
Failure Analysis
Spc
Manufacturing
Jmp
Semiconductors
Engineering
Cross Functional Team Leadership
Process Simulation
Fmea
Mems
Metrology
Ic
Yield
Semiconductor Industry
Product Engineering
Silicon
Characterization
Pcb Design
Product Development
Autocad
Powerpoint
Harvard Graphics
Quality Assurance
Microsoft Excel
Excel
Failure Mode and Effects Analysis
Failure Analysis
Spc
Manufacturing
Jmp
Semiconductors
Engineering
Cross Functional Team Leadership
Process Simulation
Fmea
Mems
Metrology
Ic
Yield
Semiconductor Industry
Product Engineering
Silicon
Characterization
Pcb Design
Product Development
Autocad
Powerpoint
Harvard Graphics
Quality Assurance
Microsoft Excel
Excel
Failure Mode and Effects Analysis
Languages:
Tagalog
Loreto Cantillep
view sourceUs Patents
-
Electrically Interconnected Stacked Die Assemblies
view source -
US Patent:8629543, Jan 14, 2014
-
Filed:Oct 27, 2010
-
Appl. No.:12/913604
-
Inventors:Simon J. S. McElrea - Scotts Valley CA, US
Scott McGrath - Scotts Valley CA, US
Terrence Caskey - Santa Cruz CA, US
Scott Jay Crane - Aromas CA, US
Marc E. Robinson - San Jose CA, US
Loreto Cantillep - San Jose CA, US -
Assignee:Invensas Corporation - San Jose CA
-
International Classification:H01L 23/02
-
US Classification:257686
-
Abstract:In die stack assembly configurations successive die in the stack are offset at a die edge at which die pads are situated, and the die are interconnected by electrically conductive traces. In some embodiments the electrically conductive traces are formed of an electrically conductive polymer. An electrically insulative conformal coating is provided having openings at die pads that are electrically connected.
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Electrically Interconnected Stacked Die Assemblies
view source -
US Patent:20080303131, Dec 11, 2008
-
Filed:May 20, 2008
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Appl. No.:12/124077
-
Inventors:Simon J.S. McElrea - Scotts Valley CA, US
Scott McGrath - Scotts Valley CA, US
Terrence Caskey - Santa Cruz CA, US
Scott Jay Crane - Aromas CA, US
Marc E. Robinson - San Jose CA, US
Loreto Cantillep - San Jose CA, US -
Assignee:Vertical Circuits, Inc. - Scotts Valley CA
-
International Classification:H01L 23/02
-
US Classification:257686, 257E23001
-
Abstract:In die stack assembly configurations successive die in the stack are offset at a die edge at which die pads are situated, and the die are interconnected by electrically conductive traces. In some embodiments the electrically conductive traces are formed of an electrically conductive polymer. An electrically insulative conformal coating is provided having openings at die pads that are electrically connected.
-
Stacked Die Assembly Having Reduced Stress Electrical Interconnects
view source -
US Patent:20110272825, Nov 10, 2011
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Filed:Nov 4, 2010
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Appl. No.:12/939524
-
Inventors:Scott McGrath - Scotts Valley CA, US
Jeffrey S. Leal - Scotts Valley CA, US
Ravi Shenoy - Dublin CA, US
Loreto Cantillep - San Jose CA, US
Simon J. S. McElrea - Scotts Valley CA, US
Suzette K. Pangrle - Cupertino CA, US -
Assignee:Vertical Circuits, Inc. - Scotts Valley CA
-
International Classification:H01L 23/522
H01L 21/56 -
US Classification:257777, 438124, 257E23142, 257E21503
-
Abstract:Methods are disclosed for improving electrical interconnection in stacked die assemblies, and stacked die assemblies are disclosed having structural features formed by the methods. The resulting stacked die assemblies are characterized by having reduced electrical interconnect failure.
Loreto Cantillep
view sourcePlaxo
Loreto Cantillep
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Loreto Cantillep
view sourceVertical Circuits
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