Luigi Di Digregorio

US Patent:

6998719, Feb 14, 2006

Filed:

Jul 30, 2003

Appl. No.:

10/631471

Inventors:

John Campbell - Los Altos CA, US
Kim R. Stevens - Auburn CA, US
Luigi DiGregorio - San Jose CA, US

Assignee:

Telairity Semiconductor, Inc. - Santa Clara CA

International Classification:

H01L 23/48

US Classification:

257786, 257691, 257207, 257208

Abstract:

Techniques are provided for reducing power supply voltage drop introduced by routing conductive traces on an integrated circuit. Techniques for reducing variations in the power supply voltages received in different regions of an integrated circuit are also provided. Power supply voltages are routed within an integrated circuit across conductive traces. The conductive traces are coupled to bond pads that receive power supply voltages from an external source. Alternate ones of the traces receive a high power supply voltage Vand a low power supply voltage V. The conductive traces reduce the voltage drop in the power supply voltages by providing shorter paths to route the power supply voltages to circuit elements on the integrated circuit.

US Patent:

7462941, Dec 9, 2008

Filed:

Sep 27, 2005

Appl. No.:

11/237304

Inventors:

John Campbell - Santa Clara CA, US
Kim R. Stevens - Santa Clara CA, US
Luigi DiGregorio - Santa Clara CA, US

Assignee:

Telairity Semiconductor, Inc. - Santa Clara CA

International Classification:

H01L 23/52
H01L 23/48
H01L 29/40

US Classification:

257781, 257E2302, 257738, 257780, 257784, 257786, 438612, 174255, 174262

Abstract:

Techniques are provided for reducing the power supply voltage drop introduced by routing conductive traces on an integrated circuit. Techniques for reducing variations in the power supply voltages received in different regions of an integrated circuit are also provided. Power supply voltages are routed within an integrated circuit across conductive traces. The conductive traces are coupled to solder bumps that receive power supply voltages from an external source. Alternate ones of the traces receive a high power supply voltage Vand a low power supply voltage V. The conductive traces reduce the voltage drop in the power supply voltages by providing shorter paths to route the power supply voltages to circuit elements on the integrated circuit.

US Patent:

60469420, Apr 4, 2000

Filed:

Sep 21, 1998

Appl. No.:

9/157708

Inventors:

Yi-Ren Warry Hwang - Fremont CA
Luigi DiGregorio - Sunnyvale CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G11C 1604

US Classification:

36518905

Abstract:

An application-specific SRAM memory cell includes first and second cross-coupled inverters coupled at first and second nodes for storing a bit of information at the first node and a complement of the bit at the second node, first and second series-connected transistors for coupling a write data signal to the first node in response to a write address signal and a clock having high logical values, third, fourth and fifth series-connected transistors for coupling the second node to ground in response to the write data signal, the write address signal and the clock having high logical values, a sixth transistor for coupling the bit to a read data line in response to a read address signal having a high logical value, a seventh transistor for coupling the complement of the bit to a third node in response to the read address signal having a high logical value, an eighth transistor for coupling the read data line to a power supply terminal in response to the third node having a low logical value, and a ninth transistor for coupling the third node to the power supply terminal in response to the read data line having a low logical value. In memory structures such as register files or arrays, the eighth and ninth transistors provide an output stage that can be shared by each memory cell coupled to the read data line.

US Patent:

57740054, Jun 30, 1998

Filed:

Aug 30, 1996

Appl. No.:

8/706340

Inventors:

Hamid Partovi - Sunnyvale CA
Robert C. Burd - Santa Clara CA
Udin Salim - San Jose CA
Frederick Weber - San Jose CA
Luigi DiGregorio - Sunnyvale CA
Donald A. Draper - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H03K 3356

US Classification:

327210

Abstract:

A high-performance flip-flop circuit implementation. The flip-flop circuit comprises an "implicit" one-shot to generate a delayed clock output (407). The flip-flop comprises a delay block (405) coupled to a clock input (210). The flip-flop may be a D-type flip-flop. In a positive-edge-triggered embodiment of the flip-flop, a falling edge (540) of the delayed clock output (407) follows a rising edge (544) of a clock signal after a delay period (548). The flip-flop clocks in new data at a data input (205) in response to the clock input (210) during this delay period (548). Data is held in a storage block (450). The flip-flop has extremely good transient characteristics, especially setup and clock-to-output times. The flip-flop consumes no static power.

US Patent:

58703314, Feb 9, 1999

Filed:

Sep 26, 1997

Appl. No.:

8/939016

Inventors:

Yi-Ren Warry Hwang - Fremont CA
Luigi DiGregorio - Sunnyvale CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G11C 1100

US Classification:

365154

Abstract:

An application-specific SRAM memory cell includes first and second cross-coupled inverters coupled at first and second nodes for storing a bit of information at the first node and a complement of the bit at the second node, first and second series-connected transistors for coupling a write data signal to the first node in response to a write address signal and a clock having high logical values, third, fourth and fifth series-connected transistors for coupling the second node to ground in response to the write data signal, the write address signal and the clock having high logical values, a sixth transistor for coupling the bit to a read data line in response to a read address signal having a high logical value, a seventh transistor for coupling the complement of the bit to a third node in response to the read address signal having a high logical value, an eighth transistor for coupling the read data line to a power supply terminal in response to the third node having a low logical value, and a ninth transistor for coupling the third node to the power supply terminal in response to the read data line having a low logical value. In memory structures such as register files or arrays, the eighth and ninth transistors provide an output stage that can be shared by each memory cell coupled to the read data line.