Lynn A Warriner

US Patent:

6734716, May 11, 2004

Filed:

Sep 19, 2002

Appl. No.:

10/247127

Inventors:

Brian W. Amick - Austin TX
Lynn Warriner - Round Rock TX
Claude R. Gauthier - Cupertino CA
Tri Tran - San Leandro CA

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G05F 110

US Classification:

327530, 327538

Abstract:

A SSTL memory interface pre-driver stage that uses a voltage regulator to generate a âvirtualâ supply is provided. The âvirtualâ supply, being lower than a power supply voltage of the pre-driver stage, allows low voltage transistors to be used, thereby improving interface performance and decreasing system power consumption. The pre-driver stage uses a biasing circuit to bias the voltage regulator, formed by a transistor arranged in a source follower configuration, to generate the âvirtualâ supply off which a voltage translator stage of the pre-driver stage operates to generate an output of the pre-driver stage.

US Patent:

6774665, Aug 10, 2004

Filed:

Sep 26, 2002

Appl. No.:

10/255341

Inventors:

Brian W. Amick - Austin TX
Lynn A. Warriner - Round Rock TX
Claude R. Gauthier - Cupertino CA
Tri K. Tran - San Leanardo CA

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

H03K 1716

US Classification:

326 30, 326 86, 326 31, 327108, 327530, 327534

Abstract:

A cascode SSTL output buffer using a source follower circuit includes a biasing circuit arranged to generate a first bias signal. The source follower circuit is responsive to the first bias signal and generates a second bias signal which is then used by a cascode circuit that receives an input signal to the SSTL output buffer to drive an output signal from the SSTL output buffer.

US Patent:

6803788, Oct 12, 2004

Filed:

Sep 20, 2002

Appl. No.:

10/251087

Inventors:

Brian W. Amick - Austin TX
Lynn A. Warriner - Round Rock TX
Claude R. Gauthier - Cupertino CA
Tri Tran - San Leandro CA

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

H03K 17687

US Classification:

326 81, 326 68

Abstract:

A SSTL interface voltage translator that uses dynamic biasing to translate an input signal to an output signal is provided. The voltage translator uses a first device that, dependent on a first bias signal, causes the output signal to be pulled down, where the first bias signal is dependent on the input signal. The voltage translator also uses a second device that, dependent on a second bias signal, causes the output signal to be pulled up, where the second bias signal is dependent on the input signal.

US Patent:

6873503, Mar 29, 2005

Filed:

Sep 19, 2002

Appl. No.:

10/247082

Inventors:

Brian W. Amick - Austin TX, US
Lynn Warriner - Round Rock TX, US
Claude R. Gauthier - Cupertino CA, US
Tri Tran - San Leandro CA, US

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

H02H003/20

US Classification:

361 18, 361 911

Abstract:

A SSTL memory interface pre-driver stage that uses a voltage regulator to generate a ‘virtual’ ground reference voltage is provided. The ‘virtual’ ground voltage reference, being greater than a zero volt ground voltage, allows low voltage transistors to be used, thereby improving interface performance and decreasing system power consumption. The pre-driver stage uses a biasing circuit to bias the voltage regulator, formed by a transistor arranged in a source follower configuration, to generate the ‘virtual’ ground reference voltage off which a voltage translator stage of the pre-driver stage operates to generate an output of the pre-driver stage.

US Patent:

20020075043, Jun 20, 2002

Filed:

Dec 14, 2000

Appl. No.:

09/734373

Inventors:

Eric MacDonald - Cedar Park TX, US
Lynn Warriner - Round Rock TX, US

Assignee:

IBM Corporation

International Classification:

H03B001/00

US Classification:

327/108000

Abstract:

A circuit for use in generating a reference voltage. The circuit includes a first transistor having a first source, a first drain, a first gate, and a first body contact. The first body contact is connected to the first gate, and the first drain is connected to an upper voltage source. A second transistor having a second source, a second drain, a second gate, and a second body contact. The second body contact is connected to the second gate, and the second drain is connected to a lower voltage. The circuit also includes a first input connected to the first gate, and a second input connected to the second gate. An output connected to the first source and the second source.

US Patent:

61337994, Oct 17, 2000

Filed:

Feb 25, 1999

Appl. No.:

9/257228

Inventors:

Wesley Favors - Austin TX
Eric William MacDonald - Cedar Park TX
Subir Mukherjee - Austin TX
Lynn Albert Warriner - Round Rock TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03B 502

US Classification:

331 57

Abstract:

A voltage controlled ring oscillator (VCRO) that can operate at low voltage and provide a variable periodic output. A plurality of transistors form a ring oscillator and a selected transistor in the ring oscillator has a body which can float with respect to ground potential. The selected transistor has a threshold voltage which is controllable by a voltage applied to the transistor body. A control input is coupled to the transistor body such that the body of the transistor can be charged by the control input. Charging the body alters the threshold voltage of the transistor and thereby controls the oscillation frequency of the oscillator.