Madian S Somasundaram from 12244 Windsor Ct, Los Altos, CA 94022, age 69, Phone: (650)9478505

Circuits To Generate A Sequential Index For An Input Number In A Pre-Defined List Of Numbers
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US Patent:

7155563, Dec 26, 2006
Filed:

Jan 21, 2004
Appl. No.:

10/763020
Inventors:

Madian Somasundaram - Los Altos Hills CA, US
Assignee:

Spans Logic Inc. - Mountain View CA
International Classification:

G06F 12/00
US Classification:

711108
Abstract:

Circuits are described that can detect the presence or absence of an input number in a pre-defined list of numbers, and provide an index into the list for a matching number. The elements of the list of numbers may be individual numbers, or sets of numbers within a range of numbers.

Memory And Power Efficient Mechanism For Fast Table Lookup
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US Patent:

7162572, Jan 9, 2007
Filed:

Oct 12, 2004
Appl. No.:

10/964283
Inventors:

Madian Somasundaram - Los Altos Hills CA, US
Assignee:

Spans Logic Inc. - Mountain View CA
International Classification:

G06F 12/00
US Classification:

711108, 365 49
Abstract:

A method of implementing classification CAM functionality using primarily RAM cells is disclosed.

Data Coding System And Method
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US Patent:

7292162, Nov 6, 2007
Filed:

Jul 12, 2006
Appl. No.:

11/486173
Inventors:

Madian Somasundaram - Los Altos Hills CA, US
International Classification:

H03M 7/46
US Classification:

341 63, 341 52, 711104, 711108
Abstract:

A data coding system that compresses data and enables data, e. g. , prefix addresses, to be represented with significantly fewer memory cells when compared to conventional coding systems.

Memory And Power Efficient Mechanism For Fast Table Lookup
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US Patent:

7296113, Nov 13, 2007
Filed:

Jul 12, 2006
Appl. No.:

11/486174
Inventors:

Madian Somasundaram - Los Altos Hills CA, US
International Classification:

G06F 12/00
US Classification:

711108, 365 49
Abstract:

A method of implementing classification CAM functionality using primarily RAM cells is disclosed. The method offers significantly more table entries in a given area, or significantly less area for a given table size than conventional ternary CAMs. The method is much more power-efficient, cheaper, and offers a greater range of features than conventional CAMs.

Control Of Memory And Power Efficient Mechanism For Fast Table Lookup
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US Patent:

7296114, Nov 13, 2007
Filed:

Jul 12, 2006
Appl. No.:

11/486240
Inventors:

Madian Somasundaram - Los Altos Hills CA, US
International Classification:

G06F 12/00
US Classification:

711108, 365 49
Abstract:

A method of implementing classification CAM functionality using primarily RAM cells is disclosed. The method offers significantly more table entries in a given area, or significantly less area for a given table size than conventional ternary CAMs. The method is much more power-efficient, cheaper, and offers a greater range of features than conventional CAMs.

System And Method For Data Phase Of Memory And Power Efficient Mechanism For Fast Table Lookup
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US Patent:

7321952, Jan 22, 2008
Filed:

Jul 12, 2006
Appl. No.:

11/485744
Inventors:

Madian Somasundaram - Los Altos Hills CA, US
International Classification:

G06F 12/00
US Classification:

711108, 365 49
Abstract:

A method of implementing classification CAM functionality using primarily RAM cells is disclosed. The method offers significantly more table entries in a given area, or significantly less area for a given table size than conventional ternary CAMs. The method is much more power-efficient, cheaper, and offers a greater range of features than conventional CAMs.

Data Coding System And Method
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US Patent:

7406561, Jul 29, 2008
Filed:

Aug 20, 2007
Appl. No.:

11/841671
Inventors:

Madian Somasundaram - Los Altos Hills CA, US
International Classification:

G06F 12/00
US Classification:

711108, 365 49, 365 50
Abstract:

A data coding system that compresses data and enables data, e. g. , prefix addresses, to be represented with significantly fewer memory cells when compared to conventional coding systems.

Large Interconnect Fabrics
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US Patent:

20120250698, Oct 4, 2012
Filed:

Mar 9, 2012
Appl. No.:

13/417091
Inventors:

Madian Somasundaram - Los Altos Hills CA, US
Assignee:

Cisco Technology, Inc. - San Jose CA
International Classification:

H04L 12/56
US Classification:

370419
Abstract:

In one embodiment, a network switch includes multiple chips communicably coupled together and a buffered crossbar. Each chip is coupled to every other chip with two bi-directional serial channels and includes a slice of the buffered crossbar. One or more input ports, one or more output ports, and an input logic module are coupled to the plurality of chips, and the input logic module is configured to receive a packet of data, allocate the packet of data into one or more data fragments, and distribute the packet of data to the buffered crossbar. An output logic module is coupled to the chips and configured to retrieve the packet of data from the buffered crossbar, reconstruct the packet of data from the data fragments according to a gather scheme, and transmit the packet of data.

Madian S Somasundaram