Mahesh J Madhav

US Patent:

20110153529, Jun 23, 2011

Filed:

Dec 23, 2009

Appl. No.:

12/646541

Inventors:

Anne W. Bracy - St. Louis MO, US
Mahesh Madhav - Portland OR, US
Hong Wang - Santa Clara CA, US

International Classification:

G06F 15/18
G06N 5/02

US Classification:

706 12, 706 54

Abstract:

A method and apparatus for efficiently generating a processor architecture model that accurately predicts performance of the processor for minimizing simulation time are described. In one embodiment, the method comprises: identifying a performance benchmark of a processor; sampling a portion of a design space for the identified performance benchmark; simulating the sampled portion of the design space to generate training data; generating a processor performance model from the training data by modifying the training data to predict an entire design space; and predicting performance of the processor for the entire design space by executing the processor performance model.

US Patent:

20220197807, Jun 23, 2022

Filed:

Dec 17, 2020

Appl. No.:

17/125770

Inventors:

- Santa Clara CA, US
Stephan Jean Jourdan - Santa Clara CA, US
Mahesh Jagdish Madhav - Portland OR, US
Aarti Chandrashekhar - Santa Clara CA, US

International Classification:

G06F 12/0862
G06F 12/128
G06F 12/02
G06F 13/16

Abstract:

An apparatus configured to provide latency-aware prefetching, and related systems, methods, and computer-readable media, are disclosed. The apparatus comprises a prefetch buffer comprising at least a first entry, and the first entry comprises a memory operation prefetch request portion storing a first previous memory operation prefetch request. The apparatus further comprises a prefetch buffer replacement circuit, which is configured to select an entry of the prefetch buffer storing a previous memory operation prefetch request for replacement with a subsequent memory operation prefetch request, and to replace the previous memory operation prefetch request in the selected entry with the subsequent memory operation prefetch request.

US Patent:

20210240609, Aug 5, 2021

Filed:

Dec 11, 2020

Appl. No.:

17/119679

Inventors:

- Santa Clara CA, US
Amin Firoozshahian - Mountain View CA, US
Andreas Kleen - Portland OR, US
Mahesh Madhav - Portland OR, US
Mahesh Maddury - Santa Clara CA, US
Chandan Egbert - San Jose CA, US
Eric Gouldey - Fort Collins CO, US

International Classification:

G06F 12/02
G06F 9/50
G06F 3/06

Abstract:

Various systems and methods for computer memory overcommitment management are described herein. A system for computer memory management includes a memory device to store data and a mapping table; and a memory overcommitment circuitry to: receive a signal to move data in a first block from a memory reduction area in the memory device to a non-memory reduction area in the memory device, the memory reduction area to store data using a memory reduction technique, and the non-memory reduction area to store data without any memory reduction techniques; allocate a second block in the non-memory reduction area; copy the data in the first block to the second block; and update the mapping table to revise a pointer to point to the second block, the mapping table used to store pointers to memory device in the memory reduction area and the non-memory reduction area.

US Patent:

20200004677, Jan 2, 2020

Filed:

Jun 27, 2018

Appl. No.:

16/020444

Inventors:

- Santa Clara CA, US
Omid Azizi - Redwood City CA, US
Chandan Egbert - San Jose CA, US
David Hansen - Santa Clara CA, US
Andreas Kleen - Portland OR, US
Mahesh Maddury - Santa Clara CA, US
Mahesh Madhav - Portland OR, US
Alexandre Solomatnikov - San Carlos CA, US
John Peter Stevenson - Chicago IL, US

International Classification:

G06F 12/02
G06F 12/1009
G06F 3/06

Abstract:

Processing circuitry for computer memory management includes memory reduction circuitry to implement a memory reduction technique; and reference count information collection circuitry to: access a memory region, the memory region subject to the memory reduction technique; obtain an indication of memory reduction of the memory region; calculate metrics based on the indication of memory reduction of cache lines associated with the memory region; and provide the metrics to a system software component for use in memory management mechanisms.

US Patent:

20190354487, Nov 21, 2019

Filed:

May 15, 2018

Appl. No.:

15/980523

Inventors:

Amin Firoozshahian - Mountain View CA, US
Mahesh Madhav - Portland OR, US
Toby Opferman - Beaverton OR, US
Omid Azizi - Redwood City CA, US

International Classification:

G06F 12/1009

Abstract:

A system for computer memory management that implements a memory pool table, the memory pool table including entries that describe a plurality of memory pools, each memory pool representing a group of memory pages related by common attributes; a per-page tracking table, each entry in the per-page tracking table used to related a memory page with a memory pool of the memory pool table; and processing circuitry to: scan each entry in the per-page tracking table and, for each entry: determine an amount of memory released if the memory page related with the entry is swapped; aggregate the amount of memory for the respective memory pool related with the memory page related with the entry in the per-page tracking table, to produce a per-pool memory aggregate; and output the per-pool memory aggregate for the memory pools related with the memory pages in the per-page tracking table.

US Patent:

20190303281, Oct 3, 2019

Filed:

Mar 30, 2018

Appl. No.:

15/941468

Inventors:

Amin Firoozshahian - Mountain View CA, US
Andreas Kleen - Portland OR, US
Stephen Van Doren - Portland OR, US
Omid Azizi - Redwood City CA, US
Mahesh Madhav - Portland OR, US
Mahesh Maddury - Santa Clara CA, US
Chandan Egbert - San Jose CA, US

International Classification:

G06F 12/02
G06F 12/06

Abstract:

Various systems and methods for controlling memory traffic flow rate are described herein. A system for computer memory management, the system comprising: rate control circuitry to: receive a rate exceeded signal from monitoring circuitry, the rate exceeded signal indicating that memory traffic flow from a traffic source exceeds a threshold; receive a distress signal from a memory controller that interfaces with a memory device, the distress signal indicating that the memory device is oversubscribed; and implement throttle circuitry to throttle the memory traffic flow from the traffic source when the rate exceeded signal and the distress signal are both asserted.

US Patent:

20190213120, Jul 11, 2019

Filed:

Jan 11, 2018

Appl. No.:

15/868819

Inventors:

Omid Azizi - Redwood City CA, US
Amin Firoozshahian - Mountain View CA, US
Andreas Kleen - Portland OR, US
Mahesh Madhav - Portland OR, US
Mahesh Maddury - Santa Clara CA, US
Chandan Egbert - San Jose CA, US
Eric Gouldey - Fort Collins CO, US

International Classification:

G06F 12/02
G06F 9/50
G06F 3/06

Abstract:

Various systems and methods for computer memory overcommitment management are described herein. A system for computer memory management includes a memory device to store data and a mapping table; and a memory overcommitment circuitry to: receive a signal to move data in a first block from a memory reduction area in the memory device to a non-memory reduction area in the memory device, the memory reduction area to store data using a memory reduction technique, and the non-memory reduction area to store data without any memory reduction techniques; allocate a second block in the non-memory reduction area; copy the data in the first block to the second block; and update the mapping table to revise a pointer to point to the second block, the mapping table used to store pointers to memory device in the memory reduction area and the non-memory reduction area.

US Patent:

20190196988, Jun 27, 2019

Filed:

Dec 27, 2017

Appl. No.:

15/855798

Inventors:

- Santa Clara CA, US
Omid Azizi - Redwood City CA, US
Chandan Egbert - San Jose CA, US
Amin Firoozshahian - Mountain View CA, US
David Christopher Hansen - Portland OR, US
Andreas Kleen - Portland OR, US
Mahesh Maddury - Santa Clara CA, US
Mahesh Madhav - Portland OR, US
Ashok Raj - Portland OR, US
Alexandre Solomatnikov - San Carlos CA, US
Stephen Van Doren - Portland OR, US

International Classification:

G06F 13/16
G06F 3/06

Abstract:

Various systems and methods for computer memory management are described herein. A system includes a memory controller to: monitor utilization of a memory device, the memory device used with a memory compression technique; determine that the utilization of the memory device violates a threshold; and initiate a system interrupt to provoke a response, responsive to the utilization of the memory device violating the threshold.