Man Wei Lee

US Patent:

45076260, Mar 26, 1985

Filed:

Jun 28, 1982

Appl. No.:

6/392973

Inventors:

Chieh Chang - Belmont CA
Man S. Lee - San Mateo CA

Assignee:

GTE Lenkurt Incorporated - Phoenix AZ

International Classification:

H03C 102
H03K 700

US Classification:

332 31R

Abstract:

An integrated single-sideband modulator comprises six integrated capacitors C1-C6 and first switch means alternately connecting C1 and C2 as feedback capacitors across a differential input operational amplifier A1. The amplifier has a virtual ground potential on its inverting input terminal for causing it to operate as a voltage source and render the circuit relatively insensitive to parasitic capacitance effects associated with capacitor plates. Second switch means cooperates with A1, C1 and C2 and is responsive to 4-phase clock signals for driving input capacitors C3-C6 so as to convert first and second quadrature-phase input signal voltages into first and second electrical charge flow signals on the inverting input terminal that are a function of products of representations of the first and second voltages in switch state time intervals and associated pulse trains which have a 90. degree. phase difference therebetween and a repetitive pattern such as +1, +1, -1, -1, etc. The amplifier and feedback capacitors combine the charge signals for producing a single-sideband signal on A1's output terminal.

US Patent:

42963923, Oct 20, 1981

Filed:

Jun 30, 1980

Appl. No.:

6/164394

Inventors:

Man S. Lee - Belmont CA

Assignee:

GTE Automatic Electric Laboratories, Inc. - Northlake IL

International Classification:

H03H 1146

US Classification:

333213

Abstract:

A two terminal circuit comprising a capacitive element (with a negative capacitance of value -C/2) connected between the terminals, and an integrated capacitor (with a positive capacitance C) having one and other sides thereof alternately or periodically connected to associated sides of the element and to ground for simulating a floating bilinear resistor having a resistance R=T/C across the terminals which satifies the bilinear transformation s=(2(z-1/T)z+1). This circuit is insensitive to both top and bottom plate parasitic capacitance effects assocated with the capacitance when one terminal is connected to a voltage source and the other to a virtual ground point on the input to an operational amplifier. In alternate embodiments, the circuit simulates a grounded bilinear resistor when only one of the terminals is connected to ground, and when one terminal and one side of the capacitor are grounded. In many applications the negative capacitive element may be absorbed by a positive capacitor of larger capacitance that is connected in parallel with it in a switched capacitor circuit.

US Patent:

39900258, Nov 2, 1976

Filed:

Dec 24, 1975

Appl. No.:

5/644280

Inventors:

Man Shek Lee - Belmont CA

Assignee:

GTE Automatic Electric Laboratories Incorporated - Northlake IL

International Classification:

H03H 744

US Classification:

333 80R

Abstract:

The one-port network here includes a pair of terminals having a resistor R7 electrically connected therebetween, and a differential-input operational amplifier having an output electrically connected through a resistor R3 to a first input of the amplifier and through a resistor R4 to a second input of the amplifier. The first input of the amplifier is connected through a capacitor C5 to one terminal of the network which is electrically connected to a ground reference potential. The second input of the amplifier is also connected to ground through a resistor R6. The first and second inputs of the amplifier are electrically connected through resistor R1 and capacitor C2, respectively, to the other terminal of the network. With the initial constraint that the value of the conductance of the resistor R4 be equal to the product of the capacitance of the capacitor C2 and the conductance of the resistor R3 divided by the capacitance of the capacitor C5, the network simulates the parallel combination of an FDNR, a capacitor, and a resistor across the terminals thereof. Particular other additional relations between values of network elements cause the simulated capacitance and/or the simulated resistance to vanish in order to simulate an FDNR singularly.

US Patent:

43833055, May 10, 1983

Filed:

Dec 22, 1980

Appl. No.:

6/219035

Inventors:

Man S. Lee - Belmont CA

Assignee:

GTE Automatic Electric Laboratories, Inc. - Northlake IL

International Classification:

G06G 762
H03H 1100

US Classification:

364802

Abstract:

A circuit for simulating the parallel combination of a floating inductor and capacitor in the bilinear and LDI domains has a pair of nodes receiving an input voltage and connected to input terminals of associated first and second voltage followers. A first capacitor C1 is alternately or periodically connected across the output terminals of the voltage followers for sampling the input voltage, and connected between the output of the second voltage follower and the input terminal of an integrator including a second capacitor C2 which integrates and stores the charge voltage on C1. A third capacitor is periodically connected to the nodes for sampling the input voltage, and connected between the output terminals of the first voltage follower and the integrator for subsequently also sampling and storing the integrated voltage on C2. The sum of the input voltage and the integrated voltage that is stored by C3 is discharged to the new input voltage when C3 is again connected across the nodes. The parallel combination of a grounded inductor and capacitor is simulated by replacing one of the voltage followers with a short circuit and connecting the associated node to ground.

US Patent:

44464380, May 1, 1984

Filed:

Oct 26, 1981

Appl. No.:

6/314827

Inventors:

Chieh Chang - Belmont CA
Man S. Lee - San Mateo CA

Assignee:

GTE Automatic Electric Incorporated - Northlake IL

International Classification:

G06G 718
H03K 500
H03B 100

US Classification:

328127

Abstract:

A switched capacitor N-path filter in which all capacitors that introduce delay in the paths, in that they have memory and are characterized such that the new charge flow into each such capacitor during each commutation cycle depends on the old charge on it from the previous commutation cycle, are replaced with an associated plurality of N-commutating capacitors.

US Patent:

43756255, Mar 1, 1983

Filed:

May 21, 1981

Appl. No.:

6/265882

Inventors:

Man S. Lee - San Mateo CA

Assignee:

GTE Automatic Electric Laboratories, Inc. - Northlake IL

International Classification:

H03H 1140

US Classification:

333213

Abstract:

An integratable circuit that simulates a source resistor comprises first and second nodes for connection to a voltage source and a virtual ground, respectively; a first integrated capacitor C1; and switch means operative for alternately electrically connecting C1's top and bottom plates to the first node and ground, respectively, and to ground and the second node, respectively, during first and second non-overlapping time periods in each time interval T for charging C1 to the source voltage and discharging C1 into the second node, respectively, where T is the time interval between adjacent second time periods and f=1/T is the switching frequency for C1. The switch means also operates for making similar connections to plates of second and third capacitors C2 and C3 in different time periods of ones of successive time intervals T, both C2 and C3 sampling a source voltage in synchronism with sampling by C1 during adjacent time intervals and holding a charge voltage for a time interval T prior to being discharged into the second node. The circuit simulates a source resistor when the first node is electrically connected to the output terminal of a voltage source that is connected to ground. This circuit configuration simulates a bilinear source resistor when the capacitances are the same values and the circuit is characterized by the bilinear transformation.

US Patent:

45104670, Apr 9, 1985

Filed:

Jun 28, 1982

Appl. No.:

6/393221

Inventors:

Chieh Chang - Belmont CA
Man S. Lee - San Mateo CA

Assignee:

GTE Communication Systems Corporation - Phoenix AZ

International Classification:

H03K 102
H03K 700

US Classification:

332 31R

Abstract:

An integrated single-sideband modulator comprises six integrated capacitors C1-C6 and first switch means alternately connecting C1 and C2 as feedback capacitors across a differential input operational amplifier A1. The amplifier has a virtual ground potential on its inverting input terminal for causing it to operate as a voltage source and render the circuit relatively insensitive to parasitic capacitance effects associated with capacitor plates. Second switch means cooperates with A1, C1 and C2 and is responsive to 4-phase clock signals for driving input capacitors C3-C6 so as to convert first and second quadrature-phase input signal voltages into first and second electrical charge flow signals on the inverting input terminal that are a function of products of representations of the first and second voltages in switch state time intervals and associated pulse trains which have a 90. degree. phase difference therebetween and a repetitive pattern such as +1, +1, -1, -1, etc. The amplifier and feedback capacitors combine the charge signals for producing a single-sideband signal on A1's output terminal.

US Patent:

55812791, Dec 3, 1996

Filed:

Nov 5, 1993

Appl. No.:

8/147456

Inventors:

Chieh Chang - Belmont CA
Man S. Lee - San Mateo CA
Alex Lushtak - Los Altos CA

Assignee:

Cirrus Logic, Inc. - Fremont CA

International Classification:

G09G 536

US Classification:

345190

Abstract:

The "chip set" of a graphics adapter interface card is reduced to a monolithic integrated circuit that includes a programmable analog clock circuit for producing a video memory clock and a video dot clock. A digital graphics adapter controller is responsive to the video memory clock and the video dot clock to produce a video information stream. A random-access memory is responsive to the video information stream to produce a video display information stream, and a digital-to-analog converter is responsive to the video display information stream to convert the video display information stream to analog signals for application to a video display device.