Marc R Battyani

US Patent:

20130226764, Aug 29, 2013

Filed:

Feb 15, 2013

Appl. No.:

13/768773

Inventors:

Marc Battyani - Arlington MA, US

International Classification:

G06Q 40/04

US Classification:

705 37

Abstract:

High volume data processing systems and methods are provided to enable ultra-low latency processing and distribution of data. The systems and methods can be implemented to service primary trading houses where microsecond delays can significantly impact performance and value. According to one aspect, the systems and methods are configured to process data from a variety of market data sources in a variety of formats, while maintaining target latencies of less than 1 microsecond. A matrix of FPGA nodes is configured to provide ultra-low latencies while enabling deterministic and distributed processing. In some embodiments, the matrix can be to configured to provide consistent latencies even during microburst conditions. Further book building operations (determination of current holdings and assets) can occur under ultra-low latency timing, providing for near instantaneous risk management, management, and execution processes, even under micro-burst conditions. In further embodiments, a FPGA matrix provides a readily expandable and convertible processing platform.

US Patent:

20220342090, Oct 27, 2022

Filed:

Jul 12, 2022

Appl. No.:

17/811962

Inventors:

- Center Valley PA, US
Marc Battyani - Arlington MA, US

International Classification:

G01T 1/175
G01N 23/223
G01T 1/17
G01T 1/36

Abstract:

Disclosed is an electronic system for resetting the voltage of a charge-sensitive pre-amplifier having input from an X-ray detector and output to an ADC. The pre-amplifier gain is increased so that the RMS ADC noise is less than 1% of a representative digitized X-ray signal. The reset logic is configured to avoid loss of X-ray counts and to prevent the pre-amplifier output being outside the allowable input range of the ADC. Reset is initiated when the pre-amplifier output rises above an upper level, which is below the maximum allowable ADC input. Reset is also initiated when a pile-up event is detected, provided that such reset will not cause the pre-amplifier output to fall below the minimum allowable ADC input. At each reset a known amount of charge is removed from the pre-amplifier, and the reset time is continuously adjusted to ensure that the charge amount does not drift.

US Patent:

20190004184, Jan 3, 2019

Filed:

Aug 22, 2018

Appl. No.:

16/108199

Inventors:

Marc Battyani - Arlington MA, US

Assignee:

Olympus Scientific Solutions Americas Inc. - Waltham MA

International Classification:

G01T 1/175
G01N 23/223

Abstract:

Disclosed is a circuit for controlling the temperature and the bias voltage of a detector used by an X-ray analytical instrument. The circuit uses a single common reference voltage for the temperature measurement and for all the ADCs and DACs in the circuit, resulting in reduced drift and improved reproducibility of detector temperature and bias voltage. ADCs with a larger number of bits are used to produce precision values of the temperature, the bias voltage, and their respective setpoints. The setpoints are digitally varied until the precision setpoint values correspond to desired values of temperature and bias setpoints.

US Patent:

20170276803, Sep 28, 2017

Filed:

Mar 28, 2016

Appl. No.:

15/082647

Inventors:

Marc Battyani - Arlington MA, US

Assignee:

Olympus Scientific Solutions Americas Inc. - Waltham MA

International Classification:

G01T 1/175
G01N 23/223

Abstract:

Disclosed is an electronic system for resetting the voltage of a charge-sensitive pre-amplifier having input from an X-ray detector and output to an ADC. The pre-amplifier gain is increased so that the RMS ADC noise is less than 1% of a representative digitized X-ray signal. The reset logic is configured to avoid loss of X-ray counts and to prevent the pre-amplifier output being outside the allowable input range of the ADC. Reset is initiated when the pre-amplifier output rises above an upper level, which is below the maximum allowable ADC input. Reset is also initiated when a pile-up event is detected, provided that such reset will not cause the pre-amplifier output to fall below the minimum allowable ADC input. At each reset a known amount of charge is removed from the pre-amplifier, and the reset time is continuously adjusted to ensure that the charge amount does not drift.

US Patent:

20170227661, Aug 10, 2017

Filed:

Feb 5, 2016

Appl. No.:

15/017215

Inventors:

Marc Battyani - Arlington MA, US
Peter Hardman - Woburn MA, US

Assignee:

Olympus Scientific Solutions Americas Inc. - Waltham MA

International Classification:

G01T 7/00
G01N 23/223

Abstract:

Disclosed are circuits for automatic calibration of the gain of electronic amplification and digitization systems for use with X-ray detectors. The calibration is based on injecting predetermined pulses into the electronic system and deriving a calibration ratio based the digital value of their amplitude with the digital value of the same pulses, unamplified and digitized with a high accuracy reference ADC. All ADCs, as well as the DACs used to control the pulser amplitude are referenced to a single common reference voltage. Calibration for non-linearity of the gain is disclosed with an alternative embodiment for the same circuits.

US Patent:

20170123075, May 4, 2017

Filed:

Nov 4, 2015

Appl. No.:

14/931921

Inventors:

Marc Battyani - Arlington MA, US

Assignee:

OLYMPUS SCIENTIFIC SOLUTIONS AMERICAS INC. - Waltham MA

International Classification:

G01T 1/175
G01N 23/223

Abstract:

Disclosed is a circuit for controlling the temperature and the bias voltage of a detector used by an X-ray analytical instrument. The circuit uses a single common reference voltage for the temperature measurement and for all the ADCs and DACs in the circuit, resulting in reduced drift and improved reproducibility of detector temperature and bias voltage. ADCs with a larger number of bits are used to produce precision values of the temperature, the bias voltage, and their respective setpoints. The setpoints are digitally varied until the precision setpoint values correspond to desired values of temperature and bias setpoints.

US Patent:

20160379227, Dec 29, 2016

Filed:

Sep 12, 2016

Appl. No.:

15/263111

Inventors:

- New York NY, US
Marc Battyani - Arlington MA, US

Assignee:

NovaSparks, Inc. - New York NY

International Classification:

G06Q 30/02
H04L 29/08
G06Q 40/04

Abstract:

High volume data processing systems and methods are provided to enable ultra-low latency processing and distribution of data. The systems and methods can be implemented to service primary trading houses where microsecond delays can significantly impact performance and value. According to one aspect, the systems and methods are configured to process data from a variety of market data sources in a variety of formats, while maintaining target latencies of less than 1 microsecond. A matrix of FPGA nodes is configured to provide ultra-low latencies while enabling deterministic and distributed processing. In some embodiments, the matrix can be configured to provide consistent latencies even during microburst conditions. Further book building operations (determination of current holdings and assets) can occur under ultra-low latency timing, providing for near instantaneous risk management, management, and execution processes, even under micro-burst conditions. In further embodiments, a FPGA matrix provides a readily expandable and convertible processing platform.