Marilyn J Lang

US Patent:

57324069, Mar 24, 1998

Filed:

Sep 23, 1992

Appl. No.:

7/950979

Inventors:

Carol Elise Bassett - Cupertino CA
Robert Gregory Campbell - Santa Clara CA
Marilyn Jean Lang - Milpitas CA
Sridhar Begur - San Jose CA

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

G06F 1314

US Classification:

711104

Abstract:

A microcomputer architecture and method allows for high processing speeds. A microprocessor constitutes the central processing unit. The microprocessor comprises an on-chip cache memory and is capable of reading data in a burst mode. The central processing unit and the system memory communicate by way of a high speed host bus. The system memory is comprised of multiple buses and is capable of delivering data to the microprocessor in a burst mode at high speeds. A memory controller addresses data locations within the system memory upon receipt of a first host address from the microprocessor. Accordingly, the microprocessor can access data in the system memory at an extremely fast rate when operating in a burst mode. High speed processing is accomplished without the need for an external cache.

US Patent:

59604506, Sep 28, 1999

Filed:

Dec 24, 1992

Appl. No.:

7/997620

Inventors:

Marilyn Jean Lang - Milpitas CA
Sridhar Begur - San Jose CA
Robert Campbell - Santa Clara CA
Carol Elise Bassett - Cupertino CA

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

G06F 1202

US Classification:

711 5

Abstract:

A microcomputer system memory architecture and method allows the system memory to provide data access at high speeds in a burst mode. The architecture and method utilizes a system memory controller capable of performing the addressing of the system memory. The microprocessor and the system memory communicate via a high speed host bus. The system memory is comprised of multiple 64-bit system memory buses to permit high speed data transfer to the microprocessor in a burst mode without the need for an external cache.

US Patent:

62021206, Mar 13, 2001

Filed:

Jul 30, 1999

Appl. No.:

9/364480

Inventors:

Marilyn Jean Lang - Milpitas CA
Sridhar Begur - San Jose CA
Robert Campbell - Santa Clara CA
Carol Elise Bassett - Cupertino CA

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

G06F 1202

US Classification:

711 5

Abstract:

A microcomputer system memory architecture and method allows the system memory to provide data access at high speeds in a burst mode. The architecture and method utilizes a system memory controller capable of performing the addressing of the system memory. The microprocessor and the system memory communicate via a high speed host bus. The system memory is comprised of multiple 64-bit system memory buses to permit high speed data transfer to the microprocessor in a burst mode without the need for an external cache.

US Patent:

20150146993, May 28, 2015

Filed:

Nov 26, 2013

Appl. No.:

14/091188

Inventors:

- Santa Clara CA, US
Marilyn J. LANG - Saratoga CA, US

Assignee:

NVIDIA CORPORATION - Santa Clara CA

International Classification:

G06T 9/00
G06T 1/60

US Classification:

382233

Abstract:

A method for encoding at least one extra bit in an image compression and decompression system. The method includes accessing an input image, and compressing the input image into a compressed image using an encoder system, wherein said encoding system implements an algorithm for encoding at least one extra bit. The method further includes communicatively transferring the compressed image to a decoding system, and decompressing the compressed image into a resulting uncompressed image that is unaltered from said input image, wherein the algorithm for encoding enables the recovery of the at least one extra bit.