Mark T Armstrong

US Patent:

6800887, Oct 5, 2004

Filed:

Mar 31, 2003

Appl. No.:

10/405110

Inventors:

Cory E. Weber - Hillsboro OR
Mark Armstrong - Portland OR
Harold Kennel - Beaverton OR
Tahir Ghani - Portland OR
Paul A. Packan - Beaverton OR
Scott Thompson - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 2980

US Classification:

257285, 257287

Abstract:

Known techniques to improve metal-oxide-semiconductor field effect transistor (MOSFET) performance is to add a high stress dielectric layer to the MOSFET. The high stress dielectric layer introduces stress in the MOSFET that causes electron mobility drive current to increase. This technique increases process complexity, however, and can degrade PMOS performance. Embodiments of the present invention create dislocation loops in the MOSFET substrate to introduce stress and implants nitrogen in the substrate to control the growth of the dislocation loops so that the stress remains beneath the channel of the MOSFET.

US Patent:

6838329, Jan 4, 2005

Filed:

Mar 31, 2003

Appl. No.:

10/404878

Inventors:

Cory E. Weber - Hillsboro OR, US
Mark A. Armstrong - Portland OR, US
Stephen M. Cea - Hillsboro OR, US
Giuseppe Curello - Portland OR, US
Aaron D. Lilak - Hillsboro OR, US
Max Wei - San Jose CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 21336
H01L 218238

US Classification:

438217, 438282, 438289, 438524, 438527

Abstract:

A method and apparatus to form a high-concentration, indium-fluorine retrograde well within a substrate. The indium-fluorine retrograde well includes an indium concentration greater than about 3E18/cm3.

US Patent:

6870179, Mar 22, 2005

Filed:

Mar 31, 2003

Appl. No.:

10/404880

Inventors:

M. Reaz Shaheed - Portland OR, US
Thomas Hoffmann - Hillsboro OR, US
Mark Armstrong - Portland OR, US
Christopher P. Auth - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L029/06

US Classification:

257 29, 257 18

Abstract:

An intentional recess or indentation is created in a region of semiconductor material that will become part of a channel of a metal oxide semiconductor (MOS) transistor structure. A layer is created on a surface of the recess to induce an appropriate type of stress in the channel.

US Patent:

7045408, May 16, 2006

Filed:

May 21, 2003

Appl. No.:

10/443152

Inventors:

Thomas Hoffmann - Portland OR, US
Chris Auth - Portland OR, US
Mark Armstrong - Portland OR, US
Stephen Cea - Hillsboro OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 21/8238
H01L 21/84
H01L 21/00
H01L 21/461
H01L 21/31

US Classification:

438199, 438763, 438744, 438158

Abstract:

An integrated circuit is described that comprises a PMOS transistor and an NMOS transistor that are formed on a semiconductor substrate. A silicate glass layer is formed on only the PMOS transistor or the NMOS transistor; and an etch stop layer is formed on the silicate glass layer. Also described is a method for forming an integrated circuit. That method comprises forming a PMOS transistor structure and an NMOS transistor structure on a semiconductor substrate, forming a silicate glass layer on only the PMOS transistor structure or the NMOS transistor structure, and forming an etch stop layer on the silicate glass layer.

US Patent:

7101765, Sep 5, 2006

Filed:

Mar 31, 2004

Appl. No.:

10/815911

Inventors:

Giuseppe Curello - Portland OR, US
Thomas Hoffmann - Portland OR, US
Mark Armstrong - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 21/336

US Classification:

438296, 438938

Abstract:

A semiconductor device having high tensile stress. The semiconductor device comprises a substrate having a source region and a drain region. Each of the source region and the drain region includes a plurality of separated source sections and drain sections, respectively. A shallow trench isolation (STI) region is formed between two separated source sections of the source region and between two separated drain sections of the drain region. A gate stack is formed on the substrate. A tensile inducing layer is formed over the substrate. The tensile inducing layer covers the STI regions, the source region, the drain region, and the gate stack. The tensile inducing layer is an insulation capable of causing tensile stress in the substrate.

US Patent:

7129533, Oct 31, 2006

Filed:

Dec 31, 2003

Appl. No.:

10/750498

Inventors:

Cory E. Weber - Hillsboro OR, US
Mark A. Armstrong - Portland OR, US
Stephen M. Cea - Hillsboro OR, US
Giuseppe Curello - Portland OR, US
Aaron D. Lilak - Hillsboro OR, US
Max Wei - San Jose CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 29/80

US Classification:

257285, 438162, 438217, 257220

Abstract:

A method and apparatus to form a high-concentration, indium-fluorine retrograde well within a substrate. The indium-fluorine retrograde well includes an indium concentration greater than about 3E18/cm3.

US Patent:

7187057, Mar 6, 2007

Filed:

Aug 13, 2004

Appl. No.:

10/918802

Inventors:

Cory E. Weber - Hillsboro OR, US
Mark Armstrong - Portland OR, US
Harold Kennel - Beaverton OR, US
Tahir Ghani - Portland OR, US
Paul A. Packan - Beaverton OR, US
Scott Thompson - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 31/0312

US Classification:

257610, 257617, 257611, 257612, 257607, 257 65, 257E21334

Abstract:

Known techniques to improve metal-oxide-semiconductor field effect transistor (MOSFET) performance is to add a high stress dielectric layer to the MOSFET. The high stress dielectric layer introduces stress in the MOSFET that causes electron mobility drive current to increase. This technique increases process complexity, however, and can degrade PMOS performance. Embodiments of the present invention create dislocation loops in the MOSFET substrate to introduce stress and implants nitrogen in the substrate to control the growth of the dislocation loops so that the stress remains beneath the channel of the MOSFET.

US Patent:

7226824, Jun 5, 2007

Filed:

Aug 13, 2004

Appl. No.:

10/918818

Inventors:

Cory E. Weber - Hillsboro OR, US
Mark Armstrong - Portland OR, US
Harold Kennel - Beaverton OR, US
Tahir Ghani - Portland OR, US
Paul A. Packan - Beaverton OR, US
Scott Thompson - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 21/338

US Classification:

438174, 438181, 438194, 438197

Abstract:

Known techniques to improve metal-oxide-semiconductor field effect transistor (MOSFET) performance is to add a high stress dielectric layer to the MOSFET. The high stress dielectric layer introduces stress in the MOSFET that causes electron mobility drive current to increase. This technique increases process complexity, however, and can degrade PMOS performance. Embodiments of the present invention create dislocation loops in the MOSFET substrate to introduce stress and implants nitrogen in the substrate to control the growth of the dislocation loops so that the stress remains beneath the channel of the MOSFET.