Mark A Chambers

US Patent:

7609095, Oct 27, 2009

Filed:

May 5, 2005

Appl. No.:

11/122002

Inventors:

Gerald I. Grand - Cumming GA, US
Mark Chambers - Mission Viejo CA, US
Baobinh Truong - San Jose CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H03K 17/00

US Classification:

327 99, 327291

Abstract:

A system and method for seamlessly reprogramming clock frequencies includes a phase locked loop (PLL) that generates CPU and double data rate (DDR) clocks. A crystal is used to generate a reference clock. The CPU clock and the reference clock are inputs to a first multiplexer, and the DDR clock and reference clock are inputs to a second multiplexer. In normal operation the multiplexers provide the CPU and DDR clock signal as outputs. To reprogram the clock frequencies and reset the PLL, (1) the reference clock signal is selected to be the output of both multiplexers, so the device is running on the internal reference clock. The mux switching is synchronized with the CPU and DDR clock signals. (2) The PLL is reprogrammed, its internal voltage-controlled oscillator is reset, and the PLL is restarted at the new desired frequency. (3) When the new PLL frequency output is stable, the multiplexers are switched back to the PLL-generated CPU and DDR clocks, synchronously with the reference clock signal.