Mark D Estes

US Patent:

20070107364, May 17, 2007

Filed:

Jun 15, 2006

Appl. No.:

11/453033

Inventors:

Mark Estes - Austin TX, US
James Estes - Manor TX, US

International Classification:

E04C 2/04

US Classification:

052606000

Abstract:

An improved structural system of cooperating building components including premolded, interlocking block units having configurable interlocking components and passage configuration components. The block units are disposed end-to-end in a plurality of stacked, interlocking courses to form a configurable plurality of horizontal and vertical passageways for receiving material. The interlocking components and configuration components enable adjacent courses of the premolded block units to be vertically aligned and longitudinally interlocked. Horizontal passageways within a course are also configured for receiving material, for being fully closed to receiving material, or for being both partially closed to receiving a selected first material and partially open for receiving a selected second material, according to the orientation of the configuration and interlocking components.

US Patent:

53012844, Apr 5, 1994

Filed:

Jan 16, 1991

Appl. No.:

7/642508

Inventors:

Mark D. Estes - Austin TX
John P. Walker - Oklahoma City OK

Assignee:

Walker-Estes Corporation - Oklahoma City OK

International Classification:

G06F 1200

US Classification:

395400

Abstract:

Object spaces which mechanize higher order relationships between attributes which describe a particular problem domain. An abstract object description defined by a set of attributes and their corresponding values is transformed into a mixed-resolution, N-dimensional object space. The mixed-resolution, N-dimensional object space represents a mechanized, logically encoded expression of attribute relationships that can be visualized. The method and apparatus interleave the frame to generate an object descriptor and generate from the frame and the object descriptor, encoded names of spatial locations for each of the N dimensions of the mixed-resolution, N-dimensional, object space, conforming to a primary form of a reflected binary code. A virtual image of the N-dimensional, object space is generated from the dimensional-spatial locations and resolution-spatial locations, and attribute values corresponding to a region of the virtual image may be selected for display.

US Patent:

56806345, Oct 21, 1997

Filed:

Mar 28, 1994

Appl. No.:

8/218333

Inventors:

Mark D. Estes - Austin TX

International Classification:

G06F 1300

US Classification:

395800

Abstract:

A modular, polymorphic network interconnecting a plurality of electronically reconfigurable devices via a modular, polymorphic interconnect, to permit a fixed, physical configuration of operating hardware devices to take on a plurality of logically addressable configurations. The modular, polymorphic interconnect further permits allocation and deallocation of selected electronically reconfigurable devices for a particular logically addressable configuration. The modular, polymorphic interconnect additionally permits the logical topology of selected electronically reconfigurable devices to be configured as at least one mixed-radix, N-dimensional network. The logical topology of mixed-radix, N-dimensional networks can be dynamically changed under control for a new configuration of logical addresses for selected electronically reconfigurable devices. The modular, polymorphic interconnect also permits one or more electronically reconfigurable devices to be selected from at least one logically related set of electronically reconfigurable devices, making the resulting network system particularly well suited for a variety of purposes related to resource management.

US Patent:

57297541, Mar 17, 1998

Filed:

May 17, 1995

Appl. No.:

8/443282

Inventors:

Mark D. Estes - Austin TX

International Classification:

G06F 1300

US Classification:

395800

Abstract:

A reconfigurable, associative network apparatus and method. During a configuration phase of the associative network apparatus, active signals corresponding to wanted input patterns are configured as an associative network and distinguished from signals corresponding to unwanted input patterns; wanted input patterns can be further associated with output patterns corresponding to wanted responses. During an operational phase of a previously configured associative network, input patterns are formed from signals produced by one or a plurality of activated inputs. Selected input patterns are then filtered from a set of possible input patterns, and output patterns are obtained in response to a particular set of connections between input and output signals. An adaptive chord keyboard system, representative of a large class of polymorphic control systems, is disclosed as an illustrative embodiment permitting dynamic association of key codes to symbol sets for readily adapting to user capabilities, limitations, and preferences.

US Patent:

51894165, Feb 23, 1993

Filed:

Apr 29, 1991

Appl. No.:

7/692386

Inventors:

Mark D. Estes - Austin TX

Assignee:

Walker-Estes Corporation - Oklahoma City OK

International Classification:

H03M 1120

US Classification:

341 26

Abstract:

A chordal keyboard method and apparatus for generating a key code using a plurality of keys coupled to a controller with a first set of registers and a second set of registers. A user depresses at least one of the plurality of keys. The controller detects, which of the plurality of keys are in a depressed position and which of the plurality of keys are released from the depressed position. The controller sets in the first set of registers and sets in the second set of registers, bit locations of respective depressed keys, and clears in the second set of registers bit locations of respective released keys. When the controller detects that all of the plurality of keys are in a released position, a key code is generated which corresponds to bit locations set in the first set of registers. After generating the key code, the controller clears the first set of registers.

US Patent:

58527400, Dec 22, 1998

Filed:

Oct 15, 1997

Appl. No.:

8/951057

Inventors:

Mark D. Estes - Austin TX

International Classification:

G06F 1300

US Classification:

39580015

Abstract:

A modular, polymorphic network interconnecting a plurality of electronically reconfigurable devices via a modular, polymorphic interconnect, to permit a fixed, physical configuration of operating hardware devices to take on a plurality of logically addressable configurations. The modular, polymorphic interconnect further permits allocation and deallocation of selected electronically reconfigurable devices for a particular logically addressable configuration. The modular, polymorphic interconnect additionally permits the logical topology of selected electronically reconfigurable devices to be configured as at least one mixed-radix, N-dimensional network. The logical topology of mixed-radix, N-dimensional networks can be dynamically changed under control for a new configuration of logical addresses for selected electronically reconfigurable devices. The modular, polymorphic interconnect also permits one or more electronically reconfigurable devices to be selected from at least one logically related set of electronically reconfigurable devices, making the resulting network system particularly well suited for a variety of purposes related to resource management.