Mark Anthony Fletcher

US Patent:

63112175, Oct 30, 2001

Filed:

Jun 4, 1998

Appl. No.:

9/090603

Inventors:

Early David Ehlinger - Houston TX
Mark F. Fletcher - Houston TX

Assignee:

Compaq Computer Corporation - Houston TX

International Classification:

G06F 15173
G06F 1314

US Classification:

709226

Abstract:

A cluster administration system that is capable of handling a cluster having one or more computing devices. The number of computing devices that may be included in a cluster is limited only by practical considerations rather than software or hardware limitations. A cluster administration system may include a cluster of computing devices, one of the computing devices being an owner. The cluster further includes a resource. Direct access to the resource by the computing devices is controlled by the owner of the cluster. The cluster administration system also includes an arbiter. The arbiter and the cluster are in communication with each other and a network, the cluster providing the network with access to the storage device. The arbiter controls the admission of new computing devices to the cluster when the owner of the cluster is incapable of admitting the new computing device. Having the arbiter outside the cluster provides greater reliability.

US Patent:

20200218599, Jul 9, 2020

Filed:

Jan 9, 2019

Appl. No.:

16/243534

Inventors:

- Houston TX, US
MARK S. FLETCHER - Houston TX, US
ROBERT VOLENTINE - Houston TX, US

International Classification:

G06F 11/10
G06F 3/06

Abstract:

Systems and methods provided for verifying the data integrity of a persistent memory device, may include: initiating a boot for a system including the persistent memory device; and determining whether a data integrity check setting is enabled for the boot. Furthermore, upon determining that a smart data integrity check condition is satisfied, a data integrity check for the persistent memory device can be executed. The data integrity check can include scanning data stored in the memory locations associated with the persistent memory device to detect whether at least one uncorrectable memory error is present within the persistent memory device. In the event at least one uncorrectable memory error is detected, writing each detected uncorrectable memory error to a memory error log, and communicated the memory error log to the Operating System (OS) of the system.

US Patent:

20180365147, Dec 20, 2018

Filed:

Jul 31, 2015

Appl. No.:

15/748639

Inventors:

- Houston TX, US
David F HEINRICH - Tomball TX, US
William C HALLOWELL - Spring TX, US
Mark S FLETCHER - Houston TX, US
Justin Haanbyull PARK - Houston TX, US
David W ENGLER - Cypress TX, US

International Classification:

G06F 12/0804
G06F 11/14

Abstract:

A system and method for a computing device having a processor, a memory module including volatile memory for random access memory (RAM), and an integrated circuit to intercept an error signal from the processor, the intercept delaying a system shutdown of the computing device. Firmware is executed by the processor to copy contents of the volatile memory to a non-volatile memory during the delay of the system shutdown.