Mark Steven Hahn

US Patent:

6622290, Sep 16, 2003

Filed:

Oct 3, 2000

Appl. No.:

09/678150

Inventors:

Arnold Ginetti - Antibes, FR
Mark Steven Hahn - Milpitas CA
Harish Kriplani - Santa Clara CA
Naser Awad - San Jose CA

Assignee:

Cadence Design Systems, Inc. - San Jose CA

International Classification:

G06F 1750

US Classification:

716 6, 716 13, 716 14, 703 19, 714726

Abstract:

A method for timing verification of very large scale integrated circuits reduces required CPU speed and memory usage. The method involves steps including partitioning the circuit into a plurality of blocks and then partitioning the verification between shell path components and core path components. Timing verification is then conducted for only shell path components while core path components are abstracted or ignored. Finally, timing verification for core path components in each block completes the process for the entire design.

US Patent:

7188327, Mar 6, 2007

Filed:

Apr 11, 2003

Appl. No.:

10/411634

Inventors:

Mark Steven Hahn - Milpitas CA, US

Assignee:

Cadence Design Systems, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716 6, 716 5

Abstract:

A method for generating a model for a circuit having logic components is provided. The method includes identifying interface path logic components of the logic components so as to define shell logic, and identifying at least one of the logic components on which a constraint has been annotated so as to define constrained logic components. A subset of the logic components to preserve is then determined, the subset including the shell logic and the constrained logic components so as to define preserved logic. The model is then formed from the preserved logic. A highly accurate model can thus be created, while reducing computational and memory requirements. On-the-fly regeneration of the model is also possible, as is dominant path logic preservation.

US Patent:

8407228, Mar 26, 2013

Filed:

Mar 26, 2010

Appl. No.:

12/748196

Inventors:

Mark Hahn - Fremont CA, US
Laurent Volpe - San Jose CA, US
Guruprasad G. Rao - Pleasanton CA, US

Assignee:

Cadence Design Systems, Inc - San Jose CA

International Classification:

G06F 17/30

US Classification:

707745, 716104

Abstract:

Disclosed is an improved approach for managing, tracking, and querying hierarchical data in layouts. According to some aspects, hierarchical grids are employed utilizing a scheme that organizes physical objects into a set of gradually refined grids that avoids the need to maintain duplicates while enhancing the desirable characteristics of existing schemes, including fast query times, fast data structure initialization and reduced memory footprint. Each grid-cell may be further partitioned into sub-containers to more efficiently provide space pruning during query operations. According to one approach, structures maintained to track existence of objects in a descendent hierarchy.

US Patent:

8413087, Apr 2, 2013

Filed:

Mar 26, 2010

Appl. No.:

12/748172

Inventors:

Guruprasad G. Rao - Pleasanton CA, US
Mark Hahn - Fremont CA, US
Laurent Volpe - San Jose CA, US

Assignee:

Cadence Design Systems, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716105

Abstract:

Disclosed is an improved approach for managing, tracking, and querying hierarchical data in layouts. According to some aspects, hierarchical grids are employed utilizing a scheme that organizes physical objects into a set of gradually refined grids that avoids the need to maintain duplicates while enhancing the desirable characteristics of existing schemes, including fast query times, fast data structure initialization and reduced memory footprint. Each grid-cell may be further partitioned into sub-containers to more efficiently provide space pruning during query operations. According to one approach, structures maintained to track existence of objects in a descendent hierarchy.

US Patent:

8413093, Apr 2, 2013

Filed:

Dec 23, 2010

Appl. No.:

12/978302

Inventors:

Guruprasad G. Rao - Pleasanton CA, US
Mark Hahn - Fremont CA, US
Laurent Volpe - San Jose CA, US

Assignee:

Cadence Design Systems, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716110

Abstract:

Disclosed is an improved approach for managing, tracking, and querying hierarchical data in layouts. According to some aspects, hierarchical grids are employed utilizing a scheme that organizes physical objects into a set of gradually refined grids that avoids the need to maintain duplicates while enhancing the desirable characteristics of existing schemes, including fast query times, fast data structure initialization and reduced memory footprint. Each grid-cell may be further partitioned into sub-containers to more efficiently provide space pruning during query operations. According to one approach, structures maintained to track existence of objects in a descendent hierarchy.

US Patent:

8453091, May 28, 2013

Filed:

Dec 23, 2010

Appl. No.:

12/978216

Inventors:

Guruprasad G. Rao - Pleasanton CA, US
Mark Hahn - Fremont CA, US
Laurent Volpe - San Jose CA, US

Assignee:

Cadence Design Systems, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716118

Abstract:

Disclosed is an improved approach for managing, tracking, and querying hierarchical data in layouts. According to some aspects, hierarchical grids are employed utilizing a scheme that organizes physical objects into a set of gradually refined grids that avoids the need to maintain duplicates while enhancing the desirable characteristics of existing schemes, including fast query times, fast data structure initialization and reduced memory footprint. Each grid-cell may be further partitioned into sub-containers to more efficiently provide space pruning during query operations. According to one approach, structures maintained to track existence of objects in a descendent hierarchy.

US Patent:

8453136, May 28, 2013

Filed:

Mar 6, 2007

Appl. No.:

11/682852

Inventors:

Mark Steven Hahn - Fremont CA, US
Arnold Ginetti - Antibes, FR

Assignee:

Cadence Design Systems, Inc. - San Jose CA

International Classification:

G06F 9/44
G06F 9/45
G06F 17/50

US Classification:

717168, 716100, 716105

Abstract:

A method and an apparatus are described for allowing several different applications to incrementally collaborate while making changes to a circuit design.

US Patent:

43800475, Apr 12, 1983

Filed:

Nov 24, 1980

Appl. No.:

6/209903

Inventors:

Bruce T. Eisenhard - Cupertino CA
Mark C. Hahn - San Jose CA

Assignee:

Corvus Systems, Inc. - San Jose CA

International Classification:

G06F 306
G11B 5008
G11B 5012

US Classification:

364200

Abstract:

An interface apparatus between a video tape recorder and a disc drive having a non-removable magnetic storage medium and a controller is disclosed. The video tape recorder provides memory back-up to data stored on the disc drive. The interface apparatus comprises a data bus for transferring the data between a shift register in the interface to the controller of the disc drive. The shift register transforms the parallel data from the controller to serial data when data is being written onto the VTR, and transforms the serial data from the VTR to parallel format when data is being read into the disc drive. The interface appartus has a clock for generating video signals. In addition, a circuit separates the sync and data portions of the video signal when the video signal is read from the tape of the VTR into the controller. A CRC generator checks for errors in the transmission of data to and from the video tape recorder. A control state machine which is responsive to the read/write signal from the controller generates a start bit, a data clock and shift signal to shift the shift register in its appropriate timing.