Mark S Haley

US Patent:

6355576, Mar 12, 2002

Filed:

Apr 26, 1999

Appl. No.:

09/299682

Inventors:

Mark Haley - Rio Medina TX
Delbert Parks - Bexar TX
Judy Galloway - Fair Oaks TX

Assignee:

VLSI Technology Inc. - San Jose CA

International Classification:

H01L 21461

US Classification:

438745, 438725, 438704, 438974, 438963

Abstract:

A method for cleaning bonding pads on a semiconductor device, as disclosed herein, includes treating the bonding pads with a CF and water vapor combination. In the process, the water vapor breaks up and the hydrogen from the water vapor couples to fluorine residue on the bonding pad surface creating a volatile HF vapor. In addition, fluorine from the CF exchanges with the titanium in the metallic polymer residue making the polymer more soluble for the organic strip operation which follows. Next, the resist is ashed and then an organic resist stripper is applied to the bonding pad area, thereby creating a clean bonding pad surface. Thereafter, a reliable bond wire connection can be made to the bonding pad.

US Patent:

6690083, Feb 10, 2004

Filed:

Jun 1, 2000

Appl. No.:

09/586411

Inventors:

Todd Mitchell - San Antonio TX
Mark W. Haley - Rio Medina TX

Assignee:

Koninklijke Philips Electronics N.V. - Eindhoven

International Classification:

H01L 2900

US Classification:

257538, 257536, 257537, 257516, 257518

Abstract:

The present invention is drawn to a method and a system for creating a sub-1V bandgap reference (BGR) circuit. In particular, a sub-1V BGR circuit is formed comprising a shallow trench isolation (STI) region and a poly silicon region above said STI region. The poly silicon region is formed having a first doped region longer than a second doped region. The poly silicon region as one single structure is adapted to function as a resistor and a diode coupled in series, said structure adapted to generate currents in a feedback loop to generate a BGR voltage. In forming the sub-1V BGR circuit, a silicide blocking mask (already available in the process flow for forming a standard semiconductor device) is used to prevent spacer oxide from forming above the center portion of the poly silicon region. In turn, silicide contacts can be formed away from the center portion of the poly silicon region.

US Patent:

20020028586, Mar 7, 2002

Filed:

Sep 21, 2001

Appl. No.:

09/962045

Inventors:

Mark Haley - Rio Medina TX, US
Delbert Parks - Bexar TX, US
Judy Galloway - Fair Oaks TX, US

International Classification:

H01L021/302

US Classification:

438/784000, 438/734000, 438/780000, 438/782000

Abstract:

A method for cleaning bonding pads on a semiconductor device, as disclosed herein, includes treating the bonding pads with a CFand water vapor combination. In the process, the water vapor breaks up and the hydrogen from the water vapor couples to fluorine residue on the bonding pad surface creating a volatile HF vapor. In addition, fluorine from the CFexchanges with the titanium in the metallic polymer residue making the polymer more soluble for the organic strip operation which follows. Next, the resist is ashed and then an organic resist stripper is applied to the bonding pad area, thereby creating a clean bonding pad surface. Thereafter, a reliable bond wire connection can be made to the bonding pad.

US Patent:

63067463, Oct 23, 2001

Filed:

Dec 30, 1999

Appl. No.:

9/475698

Inventors:

Mark W. Haley - Rio Medina TX
Todd Mitchell - San Antonio TX

Assignee:

Koninklijke Philips Electronics - Eindhoven

International Classification:

H01L 2144

US Classification:

438601

Abstract:

The present invention is directed to a method of forming an insulative layer over a fuse link in a semiconductor device that is sufficiently thick to encapsulate the fuse link during laser opening, thereby preventing vaporized metal from re-depositing on the fuse link. The layer is also sufficiently thin to allow the laser to penetrate the insulative layer during laser opening of the fuse. A primary dielectric layer is formed over a metal fuse link, the primary dielectric having a predetermined deposition thickness over the fuse link. The primary dielectric layer is then covered with an etch interrupting layer. The etch interrupting layer is covered with a secondary dielectric layer and a portion of the secondary dielectric layer is then removed, resulting in an interlayer dielectric (ILD) stack formed from the etch interrupting layer and the remaining secondary dielectric layer. The ILD has a selected thickness that is greater than the thickness of the primary dielectric layer. A metal layer is formed over the interlayer dielectric and then the layers over the etch interrupting layer and above the metal fuse link are then removed.

US Patent:

59532009, Sep 14, 1999

Filed:

Feb 5, 1998

Appl. No.:

9/019458

Inventors:

Mark W. Haley - Rio Medina TX
Albert H. Liu - San Antonio TX

Assignee:

VLSI Technology, Inc. - San Jose CA

International Classification:

H02N 1300

US Classification:

361234

Abstract:

An electrostatic chuck device for clamping a semiconductor wafer substrate during processing of the semiconductor wafer includes a power source, at least one negative pole, and a plurality of positive poles. Each positive pole selected from the plurality of positive poles is electrically separated from the negative pole. Also provided is a plurality of fuses, each fuse of the plurality of fuses is coupled to an associated positive pole included in the plurality of positive poles. Each fuse is further coupled to the power source. In some embodiments, each positive pole is electrically separated from the negative pole by an insulating epoxy. In other embodiments, the plurality of positive poles are connected to each other in parallel.

US Patent:

56002360, Feb 4, 1997

Filed:

Nov 1, 1994

Appl. No.:

8/333009

Inventors:

Mark W. Haley - San Antonio TX
Eric A. Sparks - San Antonio TX

Assignee:

VLAI Technology, Inc. - San Jose CA

International Classification:

G01R 104

US Classification:

3241581

Abstract:

A converter and digital channel selector device is provided which is interconnected between a source measurement unit having a plurality of output terminal connectors and a probe station having a plurality of input probe terminal connectors. The channel selector device is used to selectively connect each one of the plurality of output terminals of the source measurement unit to corresponding one of the plurality of input probe terminal connectors, respectively. The channel selector device includes a converter for generating a plurality of digital control signals and a digital channel select logic circuit which is responsive to the digital control signals for selectively connecting respective ones of a plurality of its input channel connectors connected to the plurality of output terminal connectors to any one of a plurality of its output channel connectors connected to the plurality of input probe terminal connectors.