Mark A Heap

US Patent:

6912616, Jun 28, 2005

Filed:

Nov 12, 2002

Appl. No.:

10/292144

Inventors:

Mark A. Heap - Sunnyvale CA, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F012/06

US Classification:

711 5, 711219, 711220, 36523003

Abstract:

One embodiment of the invention is a memory controller that maps a received address to a memory location in a plurality of memory banks, the memory controller comprising: circuitry for calculating a remainder from a division of the received address by a divisor, wherein the divisor is based on the number of the plurality of banks; circuitry for determining a particular bank of the plurality of banks based on the remainder and at least one bit of the received address; and circuitry for determining the memory location in the particular bank using at least a portion of the received address.

US Patent:

7509560, Mar 24, 2009

Filed:

Dec 29, 2003

Appl. No.:

10/747590

Inventors:

James W. Alexander - Hillsboro OR, US
Thomas J. Holman - Portland OR, US
Mark A. Heap - Sunnyvale CA, US
Stanley S. Kulick - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G11C 29/00

US Classification:

714763

Abstract:

According to one embodiment a computer system is disclosed. The computer system includes memory. The memory includes two or more rows, where each row has a plurality of memory devices. The computer system also includes a chipset. The chipset includes a detection/correction circuit to detect single and double symbol errors and correct single symbol errors for each memory row, and markers to maintain a log of errors within each memory row.

US Patent:

8327222, Dec 4, 2012

Filed:

Jan 15, 2009

Appl. No.:

12/354037

Inventors:

James W. Alexander - Hillsboro OR, US
Thomas J. Holman - Portland OR, US
Mark A. Heap - Sunnyvale CA, US
Stanley S. Kulick - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G11C 29/00

US Classification:

714763, 714723, 714769, 714785, 714755, 714786

Abstract:

According to one embodiment a computer system is disclosed. The computer system includes memory. The memory includes two or more rows, where each row has a plurality of memory devices. The computer system also includes a chipset. The chipset includes a detection/correction circuit to detect single and double symbol errors and correct single symbol errors for each memory row, and markers to maintain a log of errors within each memory row.

US Patent:

20010034815, Oct 25, 2001

Filed:

Feb 28, 2001

Appl. No.:

09/797494

Inventors:

Michael Dugan - Richardson TX, US
Gary Gostin - Plano TX, US
Mark Heap - Sunnyvale CA, US
Terry Huang - San Jose CA, US
Curtis McAllister - Sunnyvale CA, US
Henry Yu - San Jose CA, US

International Classification:

G06F012/08

US Classification:

711/118000, 711/145000, 711/133000

Abstract:

An apparatus and method for performing speculative directory cache tag updates for read accesses to memory is herein disclosed. A control unit for performing tag updates is coupled between the memory controller and the memory bank in a multiprocessor system that employs a directory-based coherency protocol. The control unit transmits data read from the memory bank to the memory controller while calculating the updated tag that it then writes back to the memory bank. In this manner, the memory bank busy time and memory bus traffic are reduced thereby improving the overall performance of a memory access.