Mark D Peters

US Patent:

6470289, Oct 22, 2002

Filed:

Aug 5, 1999

Appl. No.:

09/368950

Inventors:

Mark W. Peters - Houston TX
Richard H. Hodge - The Woodlands TX

Assignee:

Compaq Information Technologies Group, L.P. - Houston TX

International Classification:

G01K 308

US Classification:

702132, 374 10

Abstract:

A computer system having thermal control logic that efficiently cools the computer system. In accordance with one embodiment of the invention, the thermal control logic couples to a CPU module and a fan. The CPU module includes a pair of temperature response elements. One temperature response element located near or on the CPU core logic or die on which the CPU is fabricated. The other temperature response element is located near or on an exterior surface of the CPU module. The thermal control logic monitors the temperature of recorded by each temperature response element and controls the speed of the fan and the frequency of the CPU core clock independently. Preferably, the thermal control logic adjusts the fan speed as a function of the temperature recorded by the temperature element adjacent an exterior surface of the CPU module. The thermal control logic also adjusts the frequency of the CPU clock signal as a function of the temperature recorded by the temperature response element adjacent the CPU core. By disassociating control of the fan speed from the temperature of the CPU core, the annoyance in conventional computer systems caused fans that rapidly turn on and off or change speed rapidly is reduced.

US Patent:

6546472, Apr 8, 2003

Filed:

Dec 29, 2000

Appl. No.:

09/751165

Inventors:

Lee W. Atkinson - Houston TX
Vu T. Nguyen - San Jose CA
Mark W. Peters - Santa Clara CA

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 1206

US Classification:

711156, 711162, 713320

Abstract:

A computer system supports a fast hibernation operation to save power, while minimizing the amount of time it takes to enter the hibernation mode, and to resume normal operations. The system periodically stores data from system memory to non-volatile memory, such as a hard disk drive, during normal operations when the system is idle. The system includes activity monitors that detect when the data in memory pages is changed. The system periodically sweeps the monitors, and performs save operations to the non-volatile memory. When the system enters hibernation mode, the system determines which memory pages have been changed since the last save operation, and then saves those pages to memory. As an alternative, the system immediately can enter hibernation by supplying power to the memory pages that have not been saved since the last save operation. To implement this, independent switches under the control of the CPU of memory controller selectively turn off power to unsaved memory pages. The system can also implement a fast resume procedure by restoring the memory pages that have the highest priority, and saving the other pages in the background, or as need by the system devices.

US Patent:

6647472, Nov 11, 2003

Filed:

Feb 14, 2003

Appl. No.:

10/366925

Inventors:

Lee W. Atkinson - Houston TX
Vu T. Nguyen - San Jose CA
Mark W. Peters - Santa Clara CA

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 1216

US Classification:

711158, 711162

Abstract:

A computer system supports a fast hibernation operation to save power, while minimizing the amount of time it takes to enter the hibernation mode, and to resume normal operations. The system periodically stores data from system memory to non-volatile memory, such as a hard disk drive, during normal operations when the system is idle. The system includes activity monitors that detect when the data in memory pages is changed. The system periodically sweeps the monitors, and performs save operations to the non-volatile memory. When the system enters hibernation mode, the system determines which memory pages have been changed since the last save operation, and then saves those pages to memory. As an alternative, the system immediately can enter hibernation by supplying power to the memory pages that have not been saved since the last save operation. To implement this, independent switches under the control of the CPU of memory controller selectively turn off power to unsaved memory pages. The system can also implement a fast resume procedure by restoring the memory pages that have the highest priority, and saving the other pages in the background, or as need by the system devices.