Mark V Pierson

US Patent:

5980348, Nov 9, 1999

Filed:

May 19, 1998

Appl. No.:

9/082287

Inventors:

Michael A. Gaynes - Vestal NY
Allan O. Johnson - Johnson City NY
Ramesh R. Kodnani - Binghamton NY
Mark V. Pierson - Binghamton NY
Edward J. Tasillo - Newark Valley NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01J 918

US Classification:

445 24

Abstract:

A method for aligning a plurality of thin film transistor tiles for constructing a flat panel display. A coverplate is arranged on a coverplate support. A first layer of a bonding material is applied to at least one of a first side of each of the tiles and a surface of the coverplate on which the tiles are to be secured. The tiles are arranged on the coverplate, such that the first layer of bonding material is arranged between the tiles and the coverplate. The tiles are connected to an alignment apparatus. The tiles are aligned relative to each other and the coverplate. The tiles are at least partially secured to the coverplate.

US Patent:

6344099, Feb 5, 2002

Filed:

Sep 25, 2000

Appl. No.:

09/668141

Inventors:

Michael A. Gaynes - Vestal NY
Allan O. Johnson - Johnson City NY
Ramesh R. Kodnani - Binghamton NY
Mark V. Pierson - Binghamton NY
Edward J. Tasillo - Newark Valley NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

B32B 3100

US Classification:

156 64, 1562755, 156300

Abstract:

A system for aligning and attaching together a plurality of thin film transistor tiles for constructing a flat panel display. A coverplate loading station where a coverplate that the tiles are to be attached to is arranged on a coverplate support. A coverplate bonding material dispensing station where a bonding material for bonding the tiles to the coverplate is applied to a surface of the coverplate. A tile placement station where the tiles are arranged on the coverplate. A tile aligning and securing station where the tiles are aligned relative to each other and the coverplate by the tile aligner and where the tiles are at least partially bonded to the coverplate. A tile assembly bonding material dispensing station where a bonding material is applied to a surface of the tiles opposite the side that the coverplate is bonded to. A backplate placement station where a backplate is arranged on the tiles. A backplate aligning and securing station where the backplate is aligned with the tiles and the coverplate and at least partially secured to the tiles.

US Patent:

6358627, Mar 19, 2002

Filed:

Jan 23, 2001

Appl. No.:

09/768112

Inventors:

Joseph A. Benenati - Hopewell Junction NY
Claude L. Bertin - South Burlington VT
William T. Chen - Endicott NY
Thomas E. Dinan - San Jose CA
Wayne F. Ellis - Jericho VT
Wayne J. Howell - Williston VT
John U. Knickerbocker - Hopewell Junction NY
Mark V. Pierson - Binghamton NY
William R. Tonti - Essex Junction NY
Jerzy M. Zalesinski - Essex Junction NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2144

US Classification:

428612, 438613, 438666

Abstract:

An integrated circuit assembly has pads of a chip electrically connected to pads of a substrate with rolling metal balls. A pliable material bonds the balls in movable contact with pads of the chip and substrate. Because the balls are relatively free to move, thermal expansion differences that would ordinarily cause enormous stresses in the attached joints of the prior art, simply cause rolling of the balls of the present invention, avoiding thermal stress altogether. Reliability of the connections is substantially improved as compared with C4 solder bumps, and chips can be safely directly mounted to such substrates as PC boards, despite substantial thermal mismatch.

US Patent:

6399892, Jun 4, 2002

Filed:

Sep 19, 2000

Appl. No.:

09/665365

Inventors:

Cynthia Susan Milkovich - Vestal NY
Mark Vincent Pierson - Binghamton NY
Charles Gerard Woychik - Vestal NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H05K 100

US Classification:

174258, 174260, 174263

Abstract:

A multilayer CTE compensated chip interposer for connecting a semiconductor chip to a laminate chip carrier. A first dielectric layer, on the chip side of the interposer, is made of a stiff, high elastic modulus, material, such as a ceramic material, with a CTE closely matching the CTE of the chip. A second dielectric layer, on the laminate chip carrier side of the interposer, is made of resilient, low elastic modulus, material with metallurgy formed thereon, such as circuit board material, with a composite CTE closely matching the CTE of said chip carrier. A third dielectric intermediate layer, laminated between said first and second layers, is made of a low elastic modulus material with metallurgy formed thereon, such as a Teflon/glass particle material, with a composite CTE between the CTEs of said first and second layers.

US Patent:

6429384, Aug 6, 2002

Filed:

Jun 7, 2000

Appl. No.:

09/588836

Inventors:

Robert M. Japp - Vestal NY
Mark V. Pierson - Binghamton NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H05K 116

US Classification:

174260, 29744, 29832, 174250

Abstract:

A structure that adhesively couples a chip to an organic chip carrier. The chip is attached to a top surface of the organic chip carrier by interfacing a solder bump between a C4 solder structure on the chip and a pad on a top surface of the chip carrier. The melting temperature of the solder bump is less than the melting temperature of the C4 solder structure. A block of ferrous material is on a top surface of the chip. A temporary or permanent stiffener of ferrous material is on the top surface of the chip carrier. A permanent magnet is coupled to a bottom surface of the chip carrier. Alternatively, an electromagnetic could be utilized instead of the electromagnet. Due to the permanent magnet or the electromagnet, a magnetic force on the stiffener is directed toward the magnet and substantially flattens the first surface of the chip carrier. Similarly, a magnetic force on the block is directed toward the magnet such that the electronic component and the chip carrier are held in alignment. After the solder bump has been reflowed at a temperature between the melting temperature of the solder bump and the melting temperature of the C4 solder structure, the solder bump is reconfigured.

US Patent:

6437254, Aug 20, 2002

Filed:

Aug 24, 2001

Appl. No.:

09/938402

Inventors:

Alan Harris Crudo - Endicott NY
John Gillette Davis - Charlotte NC
Christian Robert Le Coz - Endicott NY
Mark Vincent Pierson - Binghamton NY
Amit Kumar Sarkhel - Endicott NY
Ajit Kumar Trivedi - Endicott NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01R 909

US Classification:

174267, 361803, 439 46, 439591, 324758

Abstract:

A method and apparatus for efficiently repairing or reworking a printed circuit board having a solder ball grid array thereon efficiently and at minimum cost includes the steps of drilling out a plated-through hole to sever electrical connections between a ball grid array pad on one surface of the printed circuit board and internal circuits and circuits on an opposite surface of the printed circuit board; inserting a pin having an insulated sleeve surrounding a portion thereof into the drilled-out hole, the pin having attached to one end a wire for attachment to the ball grid array on one surface of the printed circuit board and a post at the other end of the pin for attachment of a wire to the post; the pin having a stop along its length to control vertical positioning of the pin in the drilled-out hole, the pin referred to as a via replacement (VR) pin. Alternately, after the plated through hole is drilled out, an insulated wire may be inserted into the hole with insulation removed from the length of the wire which extends beyond one surface of the printed circuit board. The bare length of wire is bent parallel to the surface of the printed circuit board and attached thereto by a solder reflow process.

US Patent:

6487461, Nov 26, 2002

Filed:

Jun 9, 2000

Appl. No.:

09/590280

Inventors:

Michael A. Gaynes - Vestal NY
Allan O. Johnson - Johnson City NY
Ramesh R. Kodnani - Binghamton NY
Mark V. Pierson - Binghamton NY
Edward J. Tasillo - Newark Valley NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G05B 1918

US Classification:

700 58, 700 57, 700 56, 700 54, 700 62, 700 64, 349 73, 349153, 349190, 349187, 345 88, 345589, 345903, 156104, 156106, 156 87, 156286, 455 24, 455 60

Abstract:

A method for aligning a plurality of thin film transistor tiles for constructing a flat panel display. A coverplate is arranged on a coverplate support. A first layer of a bonding material is applied to at least one of a first side of each of the tiles and a surface of the coverplate on which the tiles are to be secured. The tiles are arranged on the coverplate, such that the first layer of bonding material is arranged between the tiles and the coverplate. The tiles are connected to an alignment apparatus. The tiles are aligned relative to each other and the coverplate. The tiles are at least partially secured to the coverplate.

US Patent:

6492071, Dec 10, 2002

Filed:

Sep 26, 2000

Appl. No.:

09/670410

Inventors:

William E. Bernier - Endwell NY
Mark V. Pierson - Binghamton NY
Ajit K. Trivedi - Endicott NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G03F 900

US Classification:

430 5, 430308, 438106, 438108, 438112, 438114

Abstract:

A device and process for applying mixtures of adhesive formulations combined with solder flux such that flip chips may be rapidly encapsulated with such combinations without interfering with subsequent wafer processing steps are provided. Also provided is a wafer stencil designed in such a manner that the saw kerf lines separating individual chip dies are protected from coming into contact with the formulation. Extrusion screening using such wafer stencil is also provided.