Mark L Rea

US Patent:

6764168, Jul 20, 2004

Filed:

Mar 1, 2002

Appl. No.:

10/087539

Inventors:

Henner W. Meinhold - Fremont CA
Mark L. Rea - Hayward CA
Sachin M. Chinchwadkar - Milpitas CA
Fred J. Chetcuti - Milbrae CA
John S. Drewery - Alameda CA

Assignee:

Novellus Systems, Inc. - San Jose CA

International Classification:

B41J 2125

US Classification:

347 81

Abstract:

In one embodiment, a sensor includes two plates that form a capacitor. A droplet passing between the plates changes the capacitance of the sensor, thereby triggering an amplifier coupled to the sensor to generate an output signal. The output signal is indicative of droplet characteristics and may be used to calibrate a mechanism that dispensed the droplet.

US Patent:

7091134, Aug 15, 2006

Filed:

Jun 17, 2003

Appl. No.:

10/464279

Inventors:

Henner W. Meinhold - Fremont CA, US
Wayne Cai - Milpitas CA, US
Mark L. Rea - Hayward CA, US
Sachin M. Chinchwadkar - Milpitas CA, US

Assignee:

Novellus Systems, Inc. - San Jose CA

International Classification:

H01L 21/31

US Classification:

438758, 438 5, 438 14

Abstract:

In one embodiment, an integrated circuit (IC) fabrication material is dispensed from a print head by dividing its nozzles into several groups, and sequentially allowing each group to fire. The nozzles may be grouped based on the amounts of material they dispense. For example, the nozzles may be grouped by drop volume or drop mass. In one embodiment, an IC fabrication material is dispensed on a substrate by controlling a firing sequence of a nozzle to promote merging of material on the substrate. The firing sequence may also be altered to take into account the firing sequence of adjacent nozzles.

US Patent:

7449098, Nov 11, 2008

Filed:

Dec 17, 2003

Appl. No.:

10/739822

Inventors:

Steven T. Mayer - Lake Oswego OR, US
Jonathan D. Reid - Sherwood OR, US
Mark L. Rea - Tigard OR, US
Ismail T. Emesh - Gilbert AZ, US
Henner W. Meinhold - Fremont CA, US
John S. Drewery - Alameda CA, US

Assignee:

Novellus Systems, Inc. - San Jose CA

International Classification:

C25D 5/02
C25D 5/34
C25D 5/48
C25D 7/12

US Classification:

205118, 205123, 205182, 205210, 205221, 205222

Abstract:

A disclosed form of mechanically assisted electroplating leads to a flat, thin, overburden. In one example, an accelerator is deposited on a copper surface and mechanically removed in a simplified CMP-like apparatus. The wafer is then plated in an electrolyte containing little or no accelerating additives.

US Patent:

8158532, Apr 17, 2012

Filed:

Nov 20, 2006

Appl. No.:

11/602128

Inventors:

Steven T. Mayer - Lake Oswego OR, US
Mark L. Rea - Tigard OR, US
Richard S. Hill - Atherton CA, US
Avishai Kepten - Lake Oswego OR, US
R. Marshall Stowell - Wilsonville OR, US
Eric G. Webb - Tigard OR, US

Assignee:

Novellus Systems, Inc. - San Jose CA

International Classification:

H01L 21/302

US Classification:

438754, 438692, 438745, 438759, 216105

Abstract:

Plating accelerator is applied selectively to a substantially-unfilled wide (e. g. , low-aspect-ratio feature cavity. Then, plating of metal is conducted to fill the wide feature cavity and to form an embossed structure in which the height of a wide-feature metal protrusion over the metal-filled wide-feature cavity is higher than the height of metal over field regions. Most of the overburden metal is removed using non-contact techniques, such as chemical wet etching. Metal above the wide feature cavity protects the metal-filled wide-feature interconnect against dishing, and improved planarization techniques avoid erosion of the metal interconnect and dielectric insulating layer. In some embodiments, plating of metal onto a substrate is conducted to fill narrow (e. g. , high-aspect-ratio feature cavities) in the dielectric layer before selective application of plating accelerator and filling of the wide feature cavity.

US Patent:

8470191, Jun 25, 2013

Filed:

Aug 6, 2007

Appl. No.:

11/890790

Inventors:

Steven T. Mayer - Lake Oswego OR, US
Mark L. Rea - Tigard OR, US
Richard S. Hill - Atherton CA, US
Avishai Kepten - Lake Oswego OR, US
R. Marshall Stowell - Wilsonville OR, US
Eric G. Webb - Tigard OR, US

Assignee:

Novellus Systems, Inc. - Fremont CA

International Classification:

C23F 1/02

US Classification:

216 92, 216105, 205670

Abstract:

Plating accelerator is applied selectively to a substantially-unfilled wide (e. g. , low-aspect-ratio feature cavity. Then, plating of metal is conducted to fill the wide feature cavity and to form an embossed structure in which the height of a wide-feature metal protrusion over the metal-filled wide-feature cavity is higher than the height of metal over field regions. Most of the overburden metal is removed using non-contact techniques, such as chemical wet etching. Metal above the wide feature cavity protects the metal-filled wide-feature interconnect against dishing, and improved planarization techniques avoid erosion of the metal interconnect and dielectric insulating layer. In some embodiments, plating of metal onto a substrate is conducted to fill narrow (e. g. , high-aspect-ratio feature cavities) in the dielectric layer before selective application of plating accelerator and filling of the wide feature cavity.

US Patent:

20170011906, Jan 12, 2017

Filed:

Sep 13, 2016

Appl. No.:

15/264262

Inventors:

- Fremont CA, US
Mark L. Rea - Tigard OR, US

International Classification:

H01L 21/02
C25D 5/48
C25D 5/02
G03F 7/42
C25D 7/12
H01L 21/027
H01L 21/67
H01L 21/768
H01J 37/32
C25D 5/34

Abstract:

Certain embodiments herein relate to methods and apparatus for processing a partially fabricated semiconductor substrate in a remote plasma environment. The methods may be performed in the context of wafer level packaging (WLP) processes. The methods may include exposing the substrate to a reducing plasma to remove photoresist scum and/or oxidation from an underlying seed layer. In some cases, photoresist scum is removed through a series of plasma treatments involving exposure to an oxygen-containing plasma followed by exposure to a reducing plasma. In some embodiments, an oxygen-containing plasma is further used to strip photoresist from a substrate surface after electroplating. This plasma strip may be followed by a plasma treatment involving exposure to a reducing plasma. The plasma treatments herein may involve exposure to a remote plasma within a plasma treatment module of a multi-tool electroplating apparatus.

US Patent:

20150303065, Oct 22, 2015

Filed:

Apr 21, 2014

Appl. No.:

14/257744

Inventors:

- Fremont CA, US
Mark L. Rea - Tigard OR, US

Assignee:

Lam Research Corporation - Fremont CA

International Classification:

H01L 21/3065
C25D 5/48
C25D 7/12
H01L 21/027
H01L 21/02

Abstract:

Certain embodiments herein relate to methods and apparatus for processing a partially fabricated semiconductor substrate in a remote plasma environment. The methods may be performed in the context of wafer level packaging (WLP) processes. The methods may include exposing the substrate to a reducing plasma to remove photoresist scum and/or oxidation from an underlying seed layer. In some cases, photoresist scum is removed through a series of plasma treatments involving exposure to an oxygen-containing plasma followed by exposure to a reducing plasma. In some embodiments, an oxygen-containing plasma is further used to strip photoresist from a substrate surface after electroplating. This plasma strip may be followed by a plasma treatment involving exposure to a reducing plasma. The plasma treatments herein may involve exposure to a remote plasma within a plasma treatment module of a multi-tool electroplating apparatus.