Mark W Redekopp

US Patent:

20120198402, Aug 2, 2012

Filed:

Jan 27, 2011

Appl. No.:

13/015504

Inventors:

Mark W. Redekopp - Los Angeles CA, US

International Classification:

G06F 17/50

US Classification:

716111

Abstract:

Systems and methods for mapping state elements of digital circuits for equivalence verification are provided. One method for mapping state elements for equivalence verification between a first circuit and a second circuit includes (a) determining a first sequential depth from primary inputs and primary outputs of the first circuit and the second circuit to each state element thereof, wherein the first sequential depth is a minimum count of state elements along any path between two points of a circuit, (b) identifying and mapping first state elements of the first circuit and the second circuit having a unique first sequential depth, (c) determining a second sequential depth from the identified first state elements of the first circuit and the second circuit to the remaining state elements, (d) identifying second state elements of the first circuit and the second circuit having a unique second sequential depth, and (e) repeating (c) and (d) unless the process is no longer generating new unique mappings of state elements.

US Patent:

20150100928, Apr 9, 2015

Filed:

Aug 7, 2014

Appl. No.:

14/454386

Inventors:

- Waltham MA, US
Thomas Allen Spargo - Calorado Springs CO, US
Robert T. Narumi - Yorba Linda CA, US
Mark W. Redekopp - Los Angeles CA, US

International Classification:

G06F 17/50

US Classification:

716102

Abstract:

A system and method for reverse synthesizing an integrated circuit from a netlist. A netlist extracted from a device under review is received and converted to a connected graph. Blocks of cells are identified within the connected graph and a circuit model is formed from the blocks of cells, wherein forming includes iteratively building more complex blocks of cells from simpler blocks of cells.