Mark Quinn Scaggs

US Patent:

53768205, Dec 27, 1994

Filed:

Feb 5, 1992

Appl. No.:

7/832177

Inventors:

Harold S. Crafts - Colorado Springs CO
William W. McKinley - Fort Collins CO
Mark Q. Scaggs - Parker CO

Assignee:

NCR Corporation - Dayton OH

International Classification:

H01L 4900
H01L 2702

US Classification:

257529

Abstract:

A semiconductor structure comprising a polysilicon pad, a metal pad separated from the polysilicon pad by an insulator, and a metal via connecting the pads. A fuse is formed at the intersection of the polysilicon pad and via.

US Patent:

55369685, Jul 16, 1996

Filed:

Aug 16, 1994

Appl. No.:

8/291326

Inventors:

Harold S. Crafts - Colorado Springs CO
William W. McKinley - Fort Collins CO
Mark O. Scaggs - Parker CO

Assignee:

AT&T Global Information Solutions Company - Dayton OH
Hyundai Electronics America - Milpitas CA
Symbios Logic Inc. - Fort Collins CO

International Classification:

H01L 2900
H01L 2980

US Classification:

257529

Abstract:

A programmable read only memory (PROM) including an array of polysilicon fuse elements. The fuse array is formed within a semiconductor substrate including first and second patterned signal layers electrically insulated from one another. Each polysilicon fuse element within the array connects a first electrical conductor residing in the first patterned signal layer with a second electrical conductor residing in the second patterned signal layer. The polysilicon fuse element is in the form of a narrow strip and is folded in order to cause a current flowing through the clement to crowd, lowering the amount of current required to heat the fuse element to its melting point, i. e. the threshold current. The PROM is programmed by passing a threshold current through selected fuse elements.

US Patent:

48665673, Sep 12, 1989

Filed:

Jan 6, 1989

Appl. No.:

7/294154

Inventors:

Harold S. Crafts - Fort Collins CO
Mark Q. Scaggs - Fort Collins CO

Assignee:

NCR Corporation - Dayton OH

International Classification:

H01I 506
H01L 2702

US Classification:

361311

Abstract:

A high frequency integrated circuit channel capacitor structure comprised of interdigitated field effect transistor gate electrodes and source/drain regions of minimum dimension and respective common connection. The multiplicity of parallel connected capacitive regions between the polysilicon gate electrode and a channel region in the substrate provide precisely controlled capacitors with exceptionally low resistance. Metallization contacts to the gate polysilicon and source/drain regions at each interleaved pattern, together with minimum channel length dimensions, minimizes the capacitive resistance. A CMOS configuration is also feasible.

US Patent:

57598770, Jun 2, 1998

Filed:

Apr 14, 1997

Appl. No.:

8/839426

Inventors:

Harold S. Crafts - Colorado Springs CO
William W. McKinley - Fort Collins CO
Mark Q. Scaggs - Parker CO

Assignee:

AT&T Global Information Solutions Company - Dayton OH
Hyundai Electronics America - San Jose CA
Symbios, Inc. - Fort Collins CO

International Classification:

H01L 2182

US Classification:

438132

Abstract:

A semiconductor structure comprising a polysilicon pad, a metal pad separated from the polysilicon pad by an insulator, and a metal via connecting the pads. A fuse is formed at the intersection of the polysilicon pad and via.