Mark B Simkins

US Patent:

7542425, Jun 2, 2009

Filed:

Oct 20, 2003

Appl. No.:

10/689090

Inventors:

Kevin S. Grant - Piscataway NJ, US
Mark Benjamin Simkins - Macungie PA, US
David P. Sonnier - Austin TX, US

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

H04L 1/00

US Classification:

370236, 370410, 370469

Abstract:

Backpressure information is communicated from a physical layer device to a link layer device in a communication system by generating a flow control message in the physical layer device responsive to a detected condition relating to at least a given one of a plurality of queues of the physical layer device, and transmitting the flow control message from the physical layer device to the link layer device. The flow control message may comprises backpressure information associated with a given egress queue of the physical layer device and is transmitted from the physical layer device to the link layer device as an in-band message over an interface between the physical layer device and the link layer device. Multiple-rate traffic shaping or other types of traffic shaping may be provided responsive to the flow control message.

US Patent:

7580426, Aug 25, 2009

Filed:

Sep 28, 2006

Appl. No.:

11/536191

Inventors:

Mark Benjamin Simkins - Macungie PA, US

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

H04J 3/24

US Classification:

370474

Abstract:

Preemption techniques for use in conjunction with an interface between a physical layer device and a link layer device are disclosed. Segments associated with or comprising packets, cells or other protocol data units (PDUs) are communicated between the physical layer device and the link layer device via an interface bus. At least first and second consecutive start indicators having respective first and second data segments associated therewith are received by one of the devices from the other, and the second data segment is permitted to preempt the first data segment without signaling an interface protocol violation, subject to subsequent confirmation that the preemption is appropriate. If a number of consecutive end indicators is subsequently received that balances the number of consecutive start indicators, the preemption is confirmed as appropriate, and otherwise an interface protocol violation is signaled.

US Patent:

7680124, Mar 16, 2010

Filed:

Jul 30, 2004

Appl. No.:

10/903954

Inventors:

Jinhui Li - Macungie PA, US
Ali A. Poursepanj - Austin TX, US
Mark Benjamin Simkins - Macungie PA, US

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

H04L 12/28

US Classification:

37039531

Abstract:

A network processor or other processing device of a communication system includes scheduling circuitry configured to schedule data blocks for transmission from a plurality of users or other transmission elements in timeslots of a frame. The scheduling circuitry utilizes a weight table and a mapping table. The weight table comprises a plurality of entries, with each of the entries identifying a particular one of the transmission elements. The mapping table comprises at least one entry specifying a mapping between a particular timeslot of the frame and an entry of the weight table. The scheduling circuitry determines a particular transmission element to be scheduled in a given timeslot by accessing a corresponding mapping table entry and utilizing a resultant value to access the weight table.

US Patent:

7743196, Jun 22, 2010

Filed:

Aug 15, 2007

Appl. No.:

11/839002

Inventors:

Mark Benjamin Simkins - Macungie PA, US

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

G06F 13/14
H04L 12/28
H04J 3/24

US Classification:

710305, 710107, 370218, 37039542, 370474, 370902, 718107

Abstract:

Preemption techniques are disclosed which permit multiple high-priority packets to preempt a single low-priority packet. In one aspect, a first device is configured for communication with a second device via an interface bus. The first device comprises interface circuitry configured to receive from the second device a start indicator of a first type and a start indicator of a second type, and to allow at least one data segment associated with the start indicator of the second type to preempt at least one data segment associated with the start indicator of the first type. The start indicator of the second type may have a longer pulse width than that of the start indicator of the first type, such as a double-length pulse width. The first and second devices may comprise physical layer and link layer devices of a communication system.

US Patent:

20040210588, Oct 21, 2004

Filed:

Apr 18, 2003

Appl. No.:

10/418601

Inventors:

Mark Simkins - Allentown PA, US
Seung Yang - Allentown PA, US

International Classification:

G06F017/00

US Classification:

707/100000

Abstract:

Address lookup techniques are presented that process input data and that utilize a number of node information structures. One or more of the node information structures is part of a radix tree. A bit or bits of the input data are selected by using a next node selector from a first node information structure. The first node information structure also comprises a pointer. One or more memory accesses are performed by using at least one memory address defined at least in part by the selected one or more bits and the pointer from the first node information structure. The one or more memory accesses access another node information structure comprising another pointer. In an illustrative embodiment, this process is repeated until a resultant address is determined. Node information structures may comprise leaf/branch indicators, which indicate whether a node is a leaf or a branch. When a leaf branch indicator indicates a leaf, the resultant address is found.

US Patent:

20060117054, Jun 1, 2006

Filed:

Nov 29, 2004

Appl. No.:

10/998686

Inventors:

Jinhui Li - Macungie PA, US
Mark Simkins - Macungie PA, US
Hong Wan - Phillipsburg NJ, US

International Classification:

G06F 17/00
G06F 7/00

US Classification:

707102000

Abstract:

A network processor or other processing device of a communication system includes scheduling circuitry configured to schedule data blocks for transmission from a plurality of users or other transmission elements in timeslots of a frame. The scheduling circuitry utilizes a mapping table. The mapping table comprises at least one entry specifying a mapping between a particular timeslot of the frame and a particular one of the transmission elements. The scheduling circuitry determines a particular transmission element to be scheduled in a given timeslot by accessing a corresponding mapping table entry to identify the particular transmission element. The mapping table is stored in a compressed format in memory circuitry associated with the scheduling circuitry. More specifically, the mapping table is stored as a compressed mapping table in which a particular entry identifies one of a plurality of stored values which is processed to determine a corresponding uncompressed mapping table entry.