Mark Franklin Turner

US Patent:

7496867, Feb 24, 2009

Filed:

Apr 2, 2007

Appl. No.:

11/732092

Inventors:

Mark F. Turner - Longmont CO, US
Jonathan W. Byrn - Fort Collins CO, US
Jeffrey S. Brown - Fort Collins CO, US

Assignee:

LSI Corporation - Milpitas CA

International Classification:

G06F 17/50

US Classification:

716 2, 716 5, 716 11

Abstract:

A method of managing a cell library regarding power optimization is disclosed. The method generally includes the steps of (A) reading a plurality of first modules within a first region of a circuit design stored in a design file, (B) calculating a first merit value indicating a relative sensitivity of the first region to a power consumption, the first merit value having a range from a static power dominated value to a dynamic power dominated value and (C) creating a constraint file configured to limit a design tool to a first subset of a plurality of replacement modules based on the first merit value such that the design tool automatically optimizes the power consumption of the first region by replacing at least one of the first modules with at least one of the replacement modules within the first subset, the replacement modules residing in a library file.

US Patent:

7676716, Mar 9, 2010

Filed:

Jul 8, 2008

Appl. No.:

12/169216

Inventors:

Jeffrey S. Brown - Fort Collins CO, US
Mark F. Turner - Longmont CO, US
Marek J. Marasch - Longmont CO, US

Assignee:

LSI Corporation - Milpitas CA

International Classification:

G01R 31/28
H03K 3/289

US Classification:

714724, 714 47, 714 48, 714742, 327202, 327203

Abstract:

A method of testing a tristate element by applying a given value to the tristate, applying an opposite value to a keeper element connected at an output of the tristate, capturing a first value at a downstream position of the tristate, evaluating a second value at the output of the tristate using the first value, comparing the second value to the opposite value, and producing a failure code for the tristate when the second value is not equal to the opposite value. Then, applying the opposite value to the tristate, applying the given value to the keeper element, capturing the first value, evaluating the second value using the first value, comparing the second value to the given value, and producing a failure code for the tristate when the second value is not equal to the given value. A passing code for the tristate is produced when a failure code has not been produced.

US Patent:

7787325, Aug 31, 2010

Filed:

May 14, 2008

Appl. No.:

12/120611

Inventors:

Jeffrey S. Brown - Fort Collins CO, US
Jonathan W. Byrn - Fort Collins CO, US
Mark F. Turner - Longmont CO, US

Assignee:

LSI Corporation - Milpitas CA

International Classification:

G11C 8/00

US Classification:

36523006, 365226

Abstract:

A memory device using a plurality of enhanced row decode drivers for activating wordlines in a memory array is disclosed. Circuit design attributes of the enhanced row decode drivers are varied as a function of proximity to a source of a row address signal applied to each decode driver. The circuit variations are operable to reduce the leakage power of the driver by degrading performance thereof while maintaining required worst case timing. The worst case timing being defined by the timing and performance requirements for the most distant of the row decode driver circuits relative to the source of the applied row address signals.

US Patent:

7818695, Oct 19, 2010

Filed:

Dec 21, 2007

Appl. No.:

11/962165

Inventors:

Jonathan W. Byrn - Fort Collins CO, US
Mark F. Turner - Longmont CO, US
Jeffrey S. Brown - Fort Collins CO, US

Assignee:

LSI Corporation - Milpitas CA

International Classification:

G06F 17/50

US Classification:

716 3, 716 1, 716 2, 716 4, 716 5, 716 6

Abstract:

A method to redistribute current demand is presented. The method includes a first step of determining timing arc data for one or more timing arcs of a circuit design. The method includes a second step of checking the timing arc data for delay shift target cells. The method includes a further step of swapping a delay shift target cell with a delay shift cell.

US Patent:

7932762, Apr 26, 2011

Filed:

Dec 18, 2008

Appl. No.:

12/337628

Inventors:

Mark F. Turner - Longmont CO, US
Jeff S. Brown - Fort Collins CO, US

Assignee:

LSI Corporation - Milpitas CA

International Classification:

H03K 3/037
H03K 3/3562

US Classification:

327225, 327202, 327203, 327208, 327212, 327214, 327218, 326 93, 326 95, 326 98

Abstract:

A single-path latch, a dual-path latch, a method of operating a DFF and a library of cells. In one embodiment, the single-path latch includes: (1) a passgate coupled to the data input, (2) a feedback path coupled to the passgate, the data output coupled thereto and (3) tristate circuitry coupled to the passgate and having a single transistor pair of opposite conductivity coupled to Boolean logic gates, the Boolean logic gates configured to control operation of the single transistor pair based on the data input and a pulse clock signal to drive the feedbacks path.

US Patent:

7966592, Jun 21, 2011

Filed:

Sep 8, 2008

Appl. No.:

12/206048

Inventors:

Jeffrey S. Brown - Fort Collins CO, US
Jonathan W. Byrn - Fort Collins CO, US
Mark F. Turner - Longmont CO, US

Assignee:

LSI Corporation - Milpitas CA

International Classification:

G06F 17/50
G06F 9/455

US Classification:

716108

Abstract:

A method to analyze timing in a circuit, generally including (A) simulating reception of an input signal and a clock signal at a first flip-flop, wherein (i) the input signal has a latest transition, (ii) the input signal arrives through a first path and (iii) the clock signal has an active edge, (B) calculating a value of a time difference between the latest transition and the active edge, (C) calculating a delay between the active edge and the latest transition appearing in an output signal, wherein (i) the delay is based on a model responding to the value, (ii) the model characterizes a clock-to-output delay as a function of the time difference and (iii) the characterization covering a range of values, (D) calculating an arrival time of the latest transition at a second flip-flop through a second signal path and (E) storing the arrival time in a recording medium.

US Patent:

8115531, Feb 14, 2012

Filed:

Mar 31, 2008

Appl. No.:

12/058824

Inventors:

Jeff S. Brown - Fort Collins CO, US
Miguel A. Vilchis - San Jose CA, US
Mark F. Turner - Longmont CO, US

Assignee:

LSI Corporation - Milpitas CA

International Classification:

H03K 3/289

US Classification:

327202, 327203, 327208

Abstract:

A D flip-flop (DFF), a method of operating a DFF, a latch and a library of standard logic elements including standard logic elements corresponding to a DFF and a latch. In one embodiment, the DFF has a data input and a data output and includes: (1) a master stage passgate coupled to the data input, (2) a master stage coupled to the master stage passgate and having a hysteresis inverter with feedback transistors of opposite conductivity, (3) a slave stage passgate coupled to the master stage and (4) a slave stage coupled between the slave stage passgate and the data output and having a hysteresis inverter with feedback transistors of opposite conductivity.

US Patent:

8125815, Feb 28, 2012

Filed:

Dec 18, 2008

Appl. No.:

12/337880

Inventors:

Jeffrey S. Brown - Fort Collins CO, US
Mark F. Turner - Longmont CO, US

Assignee:

LSI Corporation - Milpitas CA

International Classification:

G11C 17/00

US Classification:

365104, 365103, 365174, 365186, 36518915, 36518902, 36523002, 365 94, 36523317

Abstract:

An apparatus and method for providing a read-only memory (ROM) bit cell having one each of a PMOS transistor and an NMOS transistor, which has reduced static and dynamic electric power losses, are described. In particular, the bit cell does not require a pre-charge transistor. The sense amplifier for determining the voltages on ROM bit lines may be a digital inverter, address decoding may be simplified since there are no timing requirements with respect to transistor pre-charge, and chips containing a plurality of ROM bit cell may be readily programmed. In one embodiment of the invention, each bit cell includes one PMOS transistor having its source in electrical connection with a voltage source, its drain connected or unconnected to a bit line, and its gate connected to an inverted version of the word line signal; and one NMOS transistor having its source connected to a lower voltage source, its drain connected or disconnected to the bit line, and its gate connected to the word line. The bit cell is programmed during the ROM generation by connecting the drain of either the PMOS (logic level 1) or the NMOS (logic level 0) to the bit line.