Marni E Nabors

US Patent:

20220285342, Sep 8, 2022

Filed:

May 26, 2022

Appl. No.:

17/825664

Inventors:

- Santa Clara CA, US
Rishabh MEHANDRU - Portland OR, US
Mauro J. KOBRINSKY - Portland OR, US
Tahir GHANI - Portland OR, US
Mark BOHR - Aloha OR, US
Marni NABORS - Portland OR, US

International Classification:

H01L 27/06
H01L 21/768
H01L 21/8234
H01L 23/522
H01L 27/088
H01L 29/66
H01L 29/78

Abstract:

Described herein are apparatuses, methods, and systems associated with a deep trench via in a three-dimensional (3D) integrated circuit (IC). The 3D IC may include a logic layer having an array of logic transistors. The 3D IC may further include one or more front-side interconnects on a front side of the 3D IC and one or more back-side interconnects on a back side of the 3D IC. The deep trench may be in the logic layer to conductively couple a front-side interconnect to a back-side interconnect. The deep trench via may be formed in a diffusion region or gate region of a dummy transistor in the logic layer. Other embodiments may be described and claimed.

US Patent:

20220262791, Aug 18, 2022

Filed:

Feb 16, 2021

Appl. No.:

17/176412

Inventors:

- Santa Clara CA, US
Sukru YEMENICIOGLU - Portland OR, US
Marni NABORS - Portland OR, US
Nikolay RYZHENKO - Beaverton OR, US
Xinning WANG - Portland OR, US
Sivakumar VENKATARAMAN - Hillsboro OR, US

International Classification:

H01L 27/088
H01L 23/50
H01L 29/06
H01L 29/78

Abstract:

Integrated circuit structures having front side signal lines and backside power delivery are described. In an example, an integrated circuit structure includes a plurality of gate lines extending over a plurality of semiconductor nanowire stack or fin channel structures within a cell boundary. A plurality of trench contacts is extending over a plurality of source or drain structures within the cell boundary, individual ones of the plurality of trench contacts alternating with individual ones of the plurality of gate lines. A first signal line, a second signal line, a third signal line, and a fourth signal line are over the plurality of gate lines and the plurality of trench contacts within the cell boundary. A backside power delivery line is coupled to one of the plurality of trench contacts within the cell boundary.

US Patent:

20200279069, Sep 3, 2020

Filed:

Dec 28, 2017

Appl. No.:

16/649588

Inventors:

- Santa Clara CA, US
Mark T. BOHR - Aloha OR, US
Ruth A. BRAIN - Portland OR, US
Marni NABORS - Portland OR, US
Sourav CHAKRAVARTY - Portland OR, US

International Classification:

G06F 30/3953
H01L 23/50
H01L 23/522

Abstract:

An integrated circuit structure includes a metal level comprising a plurality of interconnect lines along a first direction. A cell is on the metal level, wherein one or more of the plurality of interconnect lines that extend through the cell comprise a power shared track that is segmented inside the cell into one or more power segments and one or more signal segments so that both power and signals share a same track.

US Patent:

20200251464, Aug 6, 2020

Filed:

Jan 31, 2019

Appl. No.:

16/263093

Inventors:

- Santa Clara CA, US
Ranjith KUMAR - Beaverton OR, US
Marni NABORS - Portland OR, US
Quan PHAN - Happy Valley OR, US

International Classification:

H01L 27/02
H01L 27/118
H01L 23/528

Abstract:

An integrated circuit structure includes a cell on a metal level, the cell defined by a cell boundary. A plurality of substantially parallel interconnect lines are inside the cell boundary. A first power track and a second power track are both dedicated to power and are located completely inside the cell boundary without any power tracks along the cell boundary on the metal level.

US Patent:

20190378790, Dec 12, 2019

Filed:

Jun 7, 2018

Appl. No.:

16/003031

Inventors:

- Santa Clara CA, US
Mauro Kobrinsky - Portland OR, US
Marni Nabors - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 23/528
H01L 27/088
H01L 29/417
H01L 29/06
H01L 21/8234
H01L 21/768
H01L 21/762
H01L 23/31

Abstract:

Described herein are integrated circuit (IC) structures, devices, and methods associated with device layer interconnects. For example, an IC die may include a device layer including a transistor array along a semiconductor fin, and a device layer interconnect in the transistor array, wherein the device layer interconnect is in electrical contact with multiple different source/drain regions of the transistor array.

US Patent:

20190378836, Dec 12, 2019

Filed:

Jun 7, 2018

Appl. No.:

16/002723

Inventors:

- Santa Clara CA, US
Rishabh MEHANDRU - Portland OR, US
Mauro J. KOBRINSKY - Portland OR, US
Tahir GHANI - Portland OR, US
Mark BOHR - Aloha OR, US
Marni NABORS - Portland OR, US

International Classification:

H01L 27/06
H01L 21/8234
H01L 27/088
H01L 29/78
H01L 29/66
H01L 23/522
H01L 21/768

Abstract:

Described herein are apparatuses, methods, and systems associated with a deep trench via in a three-dimensional (3D) integrated circuit (IC). The 3D IC may include a logic layer having an array of logic transistors. The 3D IC may further include one or more front-side interconnects on a front side of the 3D IC and one or more back-side interconnects on a back side of the 3D IC. The deep trench may be in the logic layer to conductively couple a front-side interconnect to a back-side interconnect. The deep trench via may be formed in a diffusion region or gate region of a dummy transistor in the logic layer. Other embodiments may be described and claimed.