Martin M Bell

US Patent:

6961871, Nov 1, 2005

Filed:

Sep 18, 2001

Appl. No.:

09/954078

Inventors:

Givargis A. Danialy - San Jose CA, US
Stephen V. Pateras - San Jose CA, US
Michael C. Howells - San Jose CA, US
Martin J. Bell - Santa Clara CA, US
Charles Mc Donald - San Jose CA, US
Stephen K. Sunter - Nepean, CA

Assignee:

LogicVision, Inc. - San Jose CA

International Classification:

G06F011/00

US Classification:

714 30, 714 33, 714 37, 714 39

Abstract:

A software and hardware system and an associated methodology provides ATE-independent go/no-go testing as well as advanced failure diagnosis of integrated circuits for silicon debug, process characterization, production (volume) testing, and system diagnosis comprises an embedded test architecture designed within an integrated circuit; means for seamlessly transferring information between the integrated circuit and its external environment; and an external environment that effectuates the seamless transfer for the user to perform relevant test and diagnosis.

US Patent:

55863191, Dec 17, 1996

Filed:

Jul 27, 1994

Appl. No.:

8/281045

Inventors:

Martin J. Bell - Santa Clara CA

Assignee:

VLSI Technology, Inc. - San Jose CA

International Classification:

G06F 1560

US Classification:

395701

Abstract:

A custom netlist editor is provided in which low-level netlist editing procedures may be employed by a user to directly modify a netlist in its native format. The custom netlist editor eliminates the need for user to edit netlist cells by hand or by making a new circuit schematic. More particularly, in accordance with one embodiment of the invention, a netlist is interactively edited on a computer using a plurality of defined netlist editing procedures, the netlist representing a circuit in terms of a hierarchy of cell instances, each cell defining a predetermined circuit component, and signal nets connecting the cell instances. A plurality of user commands are defined, each having as a parameter at least one of the following: a cell name, an instance name, and a signal name. A user is prompted for a command, and a user command is input. The user command is executed by calling at least one of the defined netlist editing procedures.

US Patent:

53922972, Feb 21, 1995

Filed:

Jun 5, 1992

Appl. No.:

7/893629

Inventors:

Martin J. Bell - Santa Clara CA
Muhammad A. Samad - San Jose CA

Assignee:

VLSI Technology, Inc. - San Jose CA

International Classification:

G01R 3128

US Classification:

371 226

Abstract:

A system for generating configurations for isolation circuits that can be designed into ASIC chips such that the isolation circuits are transparent during normal operation of the host chip but allow the embedded functional blocks to be readily isolated and accessed for testing via the host chip's pads.