Martin M Frank

US Patent:

7521376, Apr 21, 2009

Filed:

Oct 26, 2005

Appl. No.:

11/259165

Inventors:

Martin M. Frank - Bronx NY, US
Steven J. Koester - Ossining NY, US
John A. Ott - Greenwood Lake NY, US
Huiling Shang - Yorktown Heights NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/469

US Classification:

438778, 438758, 438765

Abstract:

A method and structure in which Ge-based semiconductor devices such as FETs and MOS capacitors can be obtained are provided. Specifically, the present invention provides a method of forming a semiconductor device including a stack including a dielectric layer and a conductive material located on and/or within a Ge-containing material (layer or wafer) in which the surface thereof is non-oxygen chalcogen rich. By providing a non-oxygen chalcogen rich interface, the formation of undesirable interfacial compounds during and after dielectric growth is suppressed and interfacial traps are reduced in density.

US Patent:

7989902, Aug 2, 2011

Filed:

Jun 18, 2009

Appl. No.:

12/487248

Inventors:

Takashi Ando - Tuckahoe NY, US
Changhwan Choi - Yorktown Heights NY, US
Martin M. Frank - Dobbs Ferry NY, US
Vijay Narayanan - New York NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 29/76
H01L 29/94
H01L 31/062
H01L 31/113
H01L 31/119

US Classification:

257410, 257411, 257E21625

Abstract:

A stack of a high-k gate dielectric and a metal gate structure includes a lower metal layer, a scavenging metal layer, and an upper metal layer. The scavenging metal layer meets the following two criteria 1) a metal (M) for which the Gibbs free energy change of the reaction Si+2/y MO→2x/y M+SiOis positive 2) a metal that has a more negative Gibbs free energy per oxygen atom for formation of oxide than the material of the lower metal layer and the material of the upper metal layer. The scavenging metal layer meeting these criteria captures oxygen atoms as the oxygen atoms diffuse through the gate electrode toward the high-k gate dielectric. In addition, the scavenging metal layer remotely reduces the thickness of a silicon oxide interfacial layer underneath the high-k dielectric. As a result, the equivalent oxide thickness (EOT) of the total gate dielectric is reduced and the field effect transistor maintains a constant threshold voltage even after high temperature processes during CMOS integration.

US Patent:

8367496, Feb 5, 2013

Filed:

May 3, 2011

Appl. No.:

13/099790

Inventors:

Takashi Ando - Tuckahoe NY, US
Changhwan Choi - Yorktown Heights NY, US
Martin M. Frank - Dobbs Ferry NY, US
Vijay Narayanan - New York NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/8238

US Classification:

438216, 438261, 438287

Abstract:

A stack of a high-k gate dielectric and a metal gate structure includes a lower metal layer, a scavenging metal layer, and an upper metal layer. The scavenging metal layer meets the following two criteria 1) a metal (M) for which the Gibbs free energy change of the reaction Si+2/y MO→2x/y M+SiOis positive 2) a metal that has a more negative Gibbs free energy per oxygen atom for formation of oxide than the material of the lower metal layer and the material of the upper metal layer. The scavenging metal layer meeting these criteria captures oxygen atoms as the oxygen atoms diffuse through the gate electrode toward the high-k gate dielectric. In addition, the scavenging metal layer remotely reduces the thickness of a silicon oxide interfacial layer underneath the high-k dielectric. As a result, the equivalent oxide thickness (EOT) of the total gate dielectric is reduced and the field effect transistor maintains a constant threshold voltage even after high temperature processes during CMOS integration.

US Patent:

20130032886, Feb 7, 2013

Filed:

Aug 1, 2011

Appl. No.:

13/195316

Inventors:

Takashi Ando - Tuckahoe NY, US
Changhwan Choi - Edgewater NY, US
Martin M. Frank - Dobbs Ferry NY, US
Unoh Kwon - Fishkill NY, US
Vijay Narayanan - New York NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 27/092
H01L 21/8238

US Classification:

257369, 438212, 257E27062, 257E21632

Abstract:

A structure has a semiconductor substrate and an nFET and a pFET disposed upon the substrate. The pFET has a semiconductor SiGe channel region formed upon or within a surface of the semiconductor substrate and a gate dielectric having an oxide layer overlying the channel region and a high-k dielectric layer overlying the oxide layer. A gate electrode overlies the gate dielectric and has a lower metal layer abutting the high-k layer, a scavenging metal layer abutting the lower metal layer, and an upper metal layer abutting the scavenging metal layer. The metal layer scavenges oxygen from the substrate (nFET) and SiGe (pFET) interface with the oxide layer resulting in an effective reduction in Tand Vof the pFET, while scaling Tiny and maintaining Vt for the nFET, resulting in the Vof the pFET becoming closer to the Vof a similarly constructed nFET with scaled Tvalues.

US Patent:

20140001516, Jan 2, 2014

Filed:

Sep 13, 2012

Appl. No.:

13/614962

Inventors:

Takashi ANDO - Tuckahoe NY, US
Martin M. FRANK - Dobbs Ferry NY, US
Vijay NARAYANAN - New York NY, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

H01L 29/778
H01L 21/338

US Classification:

257194, 438172, 257E29246, 257E21403

Abstract:

A semiconductor structure includes a high mobility semiconductor, an interfacial oxide layer, a high dielectric constant (high-k) layer, a stack, a gate electrode, and a gate dielectric. The stack comprises a lower metal layer, a scavenging metal layer comprising a scavenging metal, and an upper metal layer formed on the scavenging metal layer. A Gibbs free energy change of a chemical reaction, in which an atom constituting the high mobility semiconductor layer that directly contacts the interfacial oxide layer combines with a metal oxide material comprising the scavenging metal and oxygen to form the scavenging metal in elemental form and oxide of the atom constituting the high mobility semiconductor layer that directly contacts the interfacial oxide layer, is positive.

US Patent:

20140004674, Jan 2, 2014

Filed:

Jun 28, 2012

Appl. No.:

13/536764

Inventors:

Takashi ANDO - Tuckahoe NY, US
Martin M. FRANK - Dobbs Ferry NY, US
Vijay NARAYANAN - New York NY, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

H01L 21/336

US Classification:

438287, 257E21409

Abstract:

A high mobility semiconductor layer is formed over a semiconductor substrate. An interfacial oxide layer is formed over the high mobility semiconductor layer. A high dielectric constant (high-k) dielectric layer is formed over the interfacial oxide layer. A stack is formed over the high-k dielectric layer. The stack comprises a lower metal layer, a scavenging metal layer comprising a scavenging metal, and an upper metal layer formed on the scavenging metal layer. A Gibbs free energy change of a chemical reaction, in which an atom constituting the high mobility semiconductor layer that directly contacts the interfacial oxide layer combines with a metal oxide material comprising the scavenging metal and oxygen to form the scavenging metal in elemental form and oxide of the atom constituting the high mobility semiconductor layer that directly contacts the interfacial oxide layer, is positive. A gate electrode and a gate dielectric are formed.

US Patent:

20140042546, Feb 13, 2014

Filed:

Aug 13, 2012

Appl. No.:

13/584156

Inventors:

Takashi Ando - Tuckahoe NY, US
Min Dai - Mahwah NJ, US
Martin M. Frank - Dobbs Ferry NY, US
Barry P. Linder - Hastings-on-Hudson NY, US
Shahab Siddiqui - White Plains NY, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

H01L 29/78
H01L 21/314
H01L 27/088

US Classification:

257368, 257411, 438763, 257E29255, 257E2706, 257E21267

Abstract:

A limited number of cycles of atomic layer deposition (ALD) of Hi-K material followed by deposition of an interlayer dielectric and application of further Hi-K material and optional but preferred annealing provides increased Hi-K material content and increased breakdown voltage for input/output (I/O) transistors compared with logic transistors formed on the same chip or wafer while providing scalability of the inversion layer of the I/O and logic transistors without significantly compromising performance or bias temperature instability (BTI) parameters.

US Patent:

20220209113, Jun 30, 2022

Filed:

Dec 29, 2020

Appl. No.:

17/136107

Inventors:

- Armonk NY, US
I-Ting Kuo - Taoyuan City, TW
Robert L. Bruce - White Plains NY, US
Martin Michael Frank - Dobbs Ferry NY, US
Hiroyuki Miyazoe - White Plains NY, US

International Classification:

H01L 45/00
H01L 27/24

Abstract:

A method for mitigating moisture driven degradation of silicon doped chalcogenides includes placing a silicon doped chalcogenide composition in a process chamber, passivating dangling silicon bonds of the silicon doped chalcogenide composition by flooding the process chamber with forming gas or with hydrogen plasma, purging the forming gas or the hydrogen plasma from the process chamber, and removing the passivated silicon doped chalcogenide composition from the process chamber.