Martin J Frank

US Patent:

6825538, Nov 30, 2004

Filed:

Nov 20, 2002

Appl. No.:

10/300365

Inventors:

Martin Michael Frank - Summit NJ
Yves Chabal - Holmdel NJ
Glen David Wilk - New Providence NJ

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

H01L 2994

US Classification:

257411, 257410, 257296

Abstract:

The present invention provides a method for manufacturing a semiconductor device comprising an insulating layer that includes a seed layer formed on a substrate. The seed layer is formed by removing hydrogen forming the substrate, depositing a seed layer precursor and exposing the precursor to excited atoms to form a seed layer on the substrate.

US Patent:

7223677, May 29, 2007

Filed:

Jun 24, 2004

Appl. No.:

10/876183

Inventors:

Martin Michael Frank - Summit NJ, US
Yves Chabal - Holmdel NJ, US
Glen David Wilk - New Providence NJ, US
Martin L. Green - Summit NJ, US

Assignee:

Agere Systems, Inc. - Allentown PA

International Classification:

H01L 21/20

US Classification:

438584

Abstract:

The present invention provides a method for manufacturing a semiconductor device comprising an insulating layer that includes a seed layer formed on a silicon substrate. The seed layer is formed by exposing a hydrogen-terminated surface of the silicon substrate in a substantially oxygen-free environment to a seed layer precursor comprising a methylated metal. Forming the insulating layer further includes depositing a dielectric material on the seed layer.

US Patent:

7521376, Apr 21, 2009

Filed:

Oct 26, 2005

Appl. No.:

11/259165

Inventors:

Martin M. Frank - Bronx NY, US
Steven J. Koester - Ossining NY, US
John A. Ott - Greenwood Lake NY, US
Huiling Shang - Yorktown Heights NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/469

US Classification:

438778, 438758, 438765

Abstract:

A method and structure in which Ge-based semiconductor devices such as FETs and MOS capacitors can be obtained are provided. Specifically, the present invention provides a method of forming a semiconductor device including a stack including a dielectric layer and a conductive material located on and/or within a Ge-containing material (layer or wafer) in which the surface thereof is non-oxygen chalcogen rich. By providing a non-oxygen chalcogen rich interface, the formation of undesirable interfacial compounds during and after dielectric growth is suppressed and interfacial traps are reduced in density.

US Patent:

7560361, Jul 14, 2009

Filed:

Aug 12, 2004

Appl. No.:

10/917055

Inventors:

Martin M. Frank - New York NY, US
Alexander Reznicek - Mount Kisco NY, US
Evgeni P. Gousev - Mahopac NY, US
Eduard A. Cartier - New York NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/447

US Classification:

438455, 438591, 438287, 257411, 257E21122

Abstract:

A method of forming a gate stack for semiconductor electronic devices utilizing wafer bonding of at least one structure containing a high-k dielectric material is provided. The method of the present invention includes a step of first selecting a first and second structure having a major surface respectively. In accordance with the present invention, at least one, or both, of the first and second structures includes at least a high-k dielectric material. Next, the major surfaces of the first and second structures are bonded together to provide a bonded structure containing at least the high-k dielectric material of a gate stack.

US Patent:

7655994, Feb 2, 2010

Filed:

Oct 26, 2005

Appl. No.:

11/259644

Inventors:

Eduard A. Cartier - New York NY, US
Mathew W. Copel - Yorktown Heights NY, US
Martin M. Frank - Bronx NY, US
Evgeni P. Gousev - Saratoga CA, US
Paul C. Jamison - Hopewell Junction NY, US
Rajarao Jammy - Austin TX, US
Barry P. Linder - Hastings-on-Hudson NY, US
Vijay Narayanan - New York NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 29/94
H01L 21/326

US Classification:

257411

Abstract:

A semiconductor structure, particularly a pFET, which includes a dielectric material that has a dielectric constant of greater than that of SiOand a Ge or Si content of greater than 50% and at least one other means for threshold/flatband voltage tuning by material stack engineering is provided. The other means contemplated in the present invention include, for example, utilizing an insulating interlayer atop the dielectric for charge fixing and/or by forming an engineered channel region. The present invention also relates to a method of fabricating such a CMOS structure.

US Patent:

7718496, May 18, 2010

Filed:

Oct 30, 2007

Appl. No.:

11/927964

Inventors:

Martin M. Frank - Dobbs Ferry NY, US
Arvind Kumar - Chappaqua NY, US
Vijay Narayanan - New York NY, US
Vamsi K. Paruchuri - Albany NY, US
Jeffrey Sleight - Ridgefield CT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/8234
H01L 21/8244

US Classification:

438275, 438595, 257E2164

Abstract:

Techniques for combining transistors having different threshold voltage requirements from one another are provided. In one aspect, a semiconductor device comprises a substrate having a first and a second nFET region, and a first and a second pFET region; a logic nFET on the substrate over the first nFET region; a logic pFET on the substrate over the first pFET region; a SRAM nFET on the substrate over the second nFET region; and a SRAM pFET on the substrate over the second pFET region, each comprising a gate stack having a metal layer over a high-K layer. The logic nFET gate stack further comprises a capping layer separating the metal layer from the high-K layer, wherein the capping layer is further configured to shift a threshold voltage of the logic nFET relative to a threshold voltage of one or more of the logic pFET, SRAM nFET and SRAM pFET.

US Patent:

7858500, Dec 28, 2010

Filed:

Apr 4, 2008

Appl. No.:

12/062972

Inventors:

Eduard A. Cartier - New York NY, US
Matthew W. Copel - Yorktown Heights NY, US
Martin M. Frank - Bronx NY, US
Evgeni P. Gousev - Saratoga CA, US
Paul C. Jamison - Hopewell Junction NY, US
Rajarao Jammy - Austin TX, US
Barry P. Linder - Hastings-on-Hudson NY, US
Vijay Narayanan - New York NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/479

US Classification:

438466

Abstract:

A semiconductor structure, particularly a pFET, which includes a dielectric material that has a dielectric constant of greater than that of SiOand a Ge or Si content of greater than 50% and at least one other means for threshold/flatband voltage tuning by material stack engineering is provided. The other means contemplated in the present invention include, for example, utilizing an insulating interlayer atop the dielectric for charge fixing and/or by forming an engineered channel region. The present invention also relates to a method of fabricating such a CMOS structure.

US Patent:

7989902, Aug 2, 2011

Filed:

Jun 18, 2009

Appl. No.:

12/487248

Inventors:

Takashi Ando - Tuckahoe NY, US
Changhwan Choi - Yorktown Heights NY, US
Martin M. Frank - Dobbs Ferry NY, US
Vijay Narayanan - New York NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 29/76
H01L 29/94
H01L 31/062
H01L 31/113
H01L 31/119

US Classification:

257410, 257411, 257E21625

Abstract:

A stack of a high-k gate dielectric and a metal gate structure includes a lower metal layer, a scavenging metal layer, and an upper metal layer. The scavenging metal layer meets the following two criteria 1) a metal (M) for which the Gibbs free energy change of the reaction Si+2/y MO→2x/y M+SiOis positive 2) a metal that has a more negative Gibbs free energy per oxygen atom for formation of oxide than the material of the lower metal layer and the material of the upper metal layer. The scavenging metal layer meeting these criteria captures oxygen atoms as the oxygen atoms diffuse through the gate electrode toward the high-k gate dielectric. In addition, the scavenging metal layer remotely reduces the thickness of a silicon oxide interfacial layer underneath the high-k dielectric. As a result, the equivalent oxide thickness (EOT) of the total gate dielectric is reduced and the field effect transistor maintains a constant threshold voltage even after high temperature processes during CMOS integration.