Martin Hopkins

US Patent:

7496673, Feb 24, 2009

Filed:

Feb 24, 2005

Appl. No.:

11/065707

Inventors:

Michael Karl Gschwind - Chappaqua NY, US
Harm Peter Hofstee - Austin TX, US
Martin E. Hopkins - Bronxville NY, US
James Allan Kahle - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 15/16

US Classification:

709230, 710308, 710 22, 712 22, 712225, 711154

Abstract:

A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network.

US Patent:

20070186077, Aug 9, 2007

Filed:

Aug 1, 2006

Appl. No.:

11/461554

Inventors:

Michael Gschwind - Chappaqua NY, US
Harm Hofstee - Austin TX, US
Martin Hopkins - Bronxville NY, US
James Kahle - Austin TX, US

International Classification:

G06F 15/00

US Classification:

712003000

Abstract:

A system and method for executing instructions utilizing a preferred slot alignment mechanism is presented. A processor architecture uses a vector register file, a shared data path, and instruction execution logic to process both single instruction multiple data (SIMD) instruction and scalar instructions. The processor architecture divides a vector into four “slots,” each including four bytes, and locates scalar data in “preferred slots” to ensure proper positioning. Instructions using the preferred slot mechanism include 1) shift and rotate instructions operating across an entire quad-word that specify a shift amount, 2) memory load and store instructions that require an address, and 3) branch instructions that use the preferred slot for branch conditions (conditional branches) and branch addresses (register-indirect branches). As a result, the processor architecture eliminates the requirement for separate issue slots, separate pipelines, and the control complexity for separate scalar units.

US Patent:

47632550, Aug 9, 1988

Filed:

Jun 16, 1987

Appl. No.:

7/065175

Inventors:

Martin E. Hopkins - Chappaqua NY
Henry S. Warren - Ossining NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 928
G06F 944

US Classification:

364300

Abstract:

A method for improving the quality of code generated by a compiler or assembler, for a target machine that has short and long forms of some of its instructions with the short forms executing faster or occupying less space. The method first determines which bits of the result of each computational instruction are significant, by a backwards pass over the program that is similar to liveness analysis. Then the significant bits thus computed are used to guide the code selection process to select the most efficient instruction that computes the correct result in all the significant bit positions.

US Patent:

49611410, Oct 2, 1990

Filed:

Dec 16, 1988

Appl. No.:

7/285459

Inventors:

Martin E. Hopkins - Chappaqua NY
Henry S. Warren - Ossining NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 945

US Classification:

364200

Abstract:

A compiler generates compiled object code from source code of a computer program in a manner that produces efficient object code for a computer with dissimilar register spaces. The technique comprising the steps of (1) generating code that references symbolic registers in which the register class is not distinguished, (2) making entries in a table denoting the context in which each symbolic register occurs and constructing an equivalence tree of symbolic registers for move instructions assigned to a same equivalence class, (3) for each equivalence class, forming the logical OR function of register usage information for all symbolic registers in the class, and for each symbolic register that appears in more than one register space context, generating new symbolic register numbers so that there is one number for each register space, and storing the numbers in said table, and (4) if a definition point of a symbolic register is encountered and that symbolic register is used in more than one register space context, inserting code in said program to either do the same operation as is done at the definition point in each register space or move a value in the symbolic register from one space to another. The improvement achieved is in object code space and time of execution.

US Patent:

56995369, Dec 16, 1997

Filed:

Apr 13, 1995

Appl. No.:

8/421272

Inventors:

Martin Edward Hopkins - Chappaqua NY
Ravindra K. Nair - Briarcliff Manor NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 938

US Classification:

395392

Abstract:

A computer processing apparatus includes a buffer called a decoded instruction buffer (DIB), which is used to store groups of commands representing instructions that can be executed in parallel. Each pattern in a DIB group may be an encoding of a long instruction termed a long decoded instruction (LDI). The DIB works in conjunction with a conventional computer processing apparatus consisting of a memory system, an instruction queue, and an instruction dispatch unit feeding into a set of execution units. When an instruction is not available in the DIB, this and subsequent instructions are fetched from the memory system into the instruction queue and executed in a conventional way. Simultaneous with the execution of instructions by the conventional apparatus, a group formatter creates a set of LDIs, each of which is an alternate encoding of a set of the original instructions which can be executed in parallel. In constructing the LDIs, the group formatter analyzes the dependency between instructions and instruction latency. Each set of LDIs constructed by the group formatter is saved in the DIB so that the next execution of the same set of instructions can be executed directly from the DIB on the full complement of functional units and will not require the effort of dependency and latency analysis.

US Patent:

55264999, Jun 11, 1996

Filed:

Dec 27, 1994

Appl. No.:

8/364833

Inventors:

David Bernstein - Haifa, IL
Martin E. Hopkins - Chappaqua NY
Michael Rodeh - Oshrat, IL

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 945

US Classification:

395375

Abstract:

An instruction scheduler for a computer, capable of speculatively scheduling load instructions by moving certain categories of load instructions in an input instruction sequence from a source block of instructions to a target block of instructions to form an output instruction sequence, the instruction scheduler comprising: logic for selecting a data-independent load instruction as a candidate for rescheduling; logic for determining whether the base register that the load instruction makes use of and/or the contents thereof meets any one of a number of conditions; logic for moving the selected load instruction from the source block to the target block in response to determination that any one of the conditions is met.