Martin T Hopkins

US Patent:

6839828, Jan 4, 2005

Filed:

Aug 14, 2001

Appl. No.:

09/929805

Inventors:

Michael Karl Gschwind - Mohegan Lake NY, US
Harm Peter Hofstee - Austin TX, US
Martin Edward Hopkins - Chappaqua NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1580

US Classification:

712 20, 712 3, 712 22, 713324

Abstract:

There is provided a processor designed to operate in a plurality of modes for processing vector and scalar instructions. Register files are each for storing scalar and vector data and address information. A parallel vector unit, coupled to the register files, includes functional units configurable to operate in a vector operation mode and a scalar operation mode. The vector unit includes an apparatus for tightly coupling the functional units to perform an operation specified by a current instruction. Under a vector operation mode, the vector unit performs, in parallel, a single vector operation on a plurality of data elements. The operations performed on the plurality of data elements are each performed by a different functional unit of the vector unit. Under a scalar operation mode, the vector unit performs a scalar operation on a data element received from the register files in a functional unit within the vector unit.

US Patent:

7051168, May 23, 2006

Filed:

Aug 28, 2001

Appl. No.:

09/940911

Inventors:

Michael K. Gschwind - Yorktown NY, US
Martin E. Hopkins - Chappaqua NY, US
H. Peter Hofstee - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/00

US Classification:

711154, 711155, 712204, 712300

Abstract:

There is provided a method for aligning and inserting data elements into a memory based upon an instruction sequence consisting of one or more alignment instructions and a single store instruction. Given a data item that includes a data element to be stored, the method includes the step of aligning the data element in another memory with respect to a predetermined position in the memory, in response to the one or more alignment instructions. A mask is dynamically generated to enable writing of memory bit lines that correspond to the aligned data element. The memory bit lines are written to the memory under a control of the mask. The generating and writing steps are performed in response to the single store instruction.

US Patent:

7496673, Feb 24, 2009

Filed:

Feb 24, 2005

Appl. No.:

11/065707

Inventors:

Michael Karl Gschwind - Chappaqua NY, US
Harm Peter Hofstee - Austin TX, US
Martin E. Hopkins - Bronxville NY, US
James Allan Kahle - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 15/16

US Classification:

709230, 710308, 710 22, 712 22, 712225, 711154

Abstract:

A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network.

US Patent:

7509457, Mar 24, 2009

Filed:

Feb 24, 2005

Appl. No.:

11/065537

Inventors:

Erik Richter Altman - Danbury CT, US
Peter George Capek - Ossining NY, US
Michael Karl Gschwind - Chappaqua NY, US
Charles Ray Johns - Austin TX, US
Harm Peter Hofstee - Austin TX, US
Martin E. Hopkins - Bronxville NY, US
James Allan Kahle - Austin TX, US
Sumedh W. Sathaye - Cary NC, US
John-David Wellman - Hopewell Junction NY, US
Ravi Nair - Briarcliff Manor NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/00

US Classification:

711119, 711147, 711150

Abstract:

A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network.

US Patent:

20070186077, Aug 9, 2007

Filed:

Aug 1, 2006

Appl. No.:

11/461554

Inventors:

Michael Gschwind - Chappaqua NY, US
Harm Hofstee - Austin TX, US
Martin Hopkins - Bronxville NY, US
James Kahle - Austin TX, US

International Classification:

G06F 15/00

US Classification:

712003000

Abstract:

A system and method for executing instructions utilizing a preferred slot alignment mechanism is presented. A processor architecture uses a vector register file, a shared data path, and instruction execution logic to process both single instruction multiple data (SIMD) instruction and scalar instructions. The processor architecture divides a vector into four “slots,” each including four bytes, and locates scalar data in “preferred slots” to ensure proper positioning. Instructions using the preferred slot mechanism include 1) shift and rotate instructions operating across an entire quad-word that specify a shift amount, 2) memory load and store instructions that require an address, and 3) branch instructions that use the preferred slot for branch conditions (conditional branches) and branch addresses (register-indirect branches). As a result, the processor architecture eliminates the requirement for separate issue slots, separate pipelines, and the control complexity for separate scalar units.

US Patent:

20080162877, Jul 3, 2008

Filed:

Mar 15, 2008

Appl. No.:

12/049324

Inventors:

Erik Richter Altman - Danbury CT, US
Peter George Capek - Ossining NY, US
Michael Karl Gschwind - Chappaqua NY, US
Charles Ray Johns - Austin TX, US
Harm Peter Hofstee - Austin TX, US
Martin E. Hopkins - Bronxville NY, US
James Allan Kahle - Austin TX, US
Sumedh W. Sathaye - Cary NC, US
John-David Wellman - Hopewell Junction NY, US
Ravi Nair - Briarcliff Manor NY, US

International Classification:

G06F 15/76
G06F 9/30

US Classification:

712 34, 712E09016

Abstract:

A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network.

US Patent:

46565825, Apr 7, 1987

Filed:

Feb 4, 1985

Appl. No.:

6/697675

Inventors:

Gregory J. Chaitin - Yorktown Heights NY
Martin E. Hopkins - Chappaqua NY
Peter W. Markstein - Yorktown Heights NY
Henry S. Warren - Ossining NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 100

US Classification:

364300

Abstract:

A method for improving the quality of code generated by a compiler in terms of execution time, object code space, or both. The method is applicable to computers that have a redundancy of instructions, in that the same operation exists in forms that operate between registers, between main storage locations, and between registers and main storage. The method selects the best form of each such instruction to use, for the context in which the instruction lies.

US Patent:

47632550, Aug 9, 1988

Filed:

Jun 16, 1987

Appl. No.:

7/065175

Inventors:

Martin E. Hopkins - Chappaqua NY
Henry S. Warren - Ossining NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 928
G06F 944

US Classification:

364300

Abstract:

A method for improving the quality of code generated by a compiler or assembler, for a target machine that has short and long forms of some of its instructions with the short forms executing faster or occupying less space. The method first determines which bits of the result of each computational instruction are significant, by a backwards pass over the program that is similar to liveness analysis. Then the significant bits thus computed are used to guide the code selection process to select the most efficient instruction that computes the correct result in all the significant bit positions.