Martin J Hopkins

US Patent:

7233998, Jun 19, 2007

Filed:

Mar 22, 2001

Appl. No.:

09/816004

Inventors:

Masakazu Suzuoki - Tokyo, JP
Takeshi Yamazaki - Tokyo, JP
Harm Peter Hofstee - Austin TX, US
Martin E. Hopkins - Bronxville NY, US
Charles Ray Johns - Austin TX, US
James Allan Kahle - Austin TX, US
Shigehiro Asano - Austin TX, US
Atsushi Kunimatsu - Kawasaki, JP

Assignee:

Sony Computer Entertainment Inc.
Kabushiki Kaisha Toshiba
International Business Machines Corporation - Armonk NY

International Classification:

G06F 15/16

US Classification:

709230, 709238

Abstract:

A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network.

US Patent:

7720982, May 18, 2010

Filed:

Mar 12, 2007

Appl. No.:

11/716845

Inventors:

Masakazu Suzuoki - Tokyo, JP
Takeshi Yamazaki - Tokyo, JP
Harm Peter Hofstee - Austin TX, US
Martin E. Hopkins - Bronxville NY, US
Charles Ray Johns - Austin TX, US
James Allan Kahle - Austin TX, US
Shigehiro Asano - Austin TX, US
Atsushi Kunimatsu - Kawasaki, JP

Assignee:

Sony Computer Entertainment Inc.
International Business Machines Corporation - Armonk NY
Kabushiki Kaisha Toshiba

International Classification:

G06F 15/16

US Classification:

709230, 709225, 710 74, 719315

Abstract:

A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network.