Masato Horiike

US Patent:

7130210, Oct 31, 2006

Filed:

Jan 13, 2005

Appl. No.:

11/034642

Inventors:

Fatima Bathul - Cupertino CA, US
Darlene Hamilton - San Jose CA, US
Masato Horiike - Sunnyvale CA, US

Assignee:

Spansion LLC - Sunnyvale CA

International Classification:

G11C 17/00

US Classification:

365100, 36518503

Abstract:

Methods of programming a wordline of multi-level flash memory cells (MLB) having three or more data levels per bit corresponding to three or more threshold voltages are provided. The present invention employs an interactive program algorithm that programs the bits of the wordline of memory cells in two programming phases, comprising a rough programming phase and a fine programming phase to achieve highly compact Vt distributions. In one example, cell bit-pairs that are to be programmed to the same program pattern are selected along a wordline. Groups of sample bits are chosen for each wordline to represent each possible program level. The sample bits are then programmed to determine a corresponding drain voltage at which each sample group is first programmed. This fast-bit drain voltage (Fvd) for each program level essentially provides a wordline specific program characterization of the Vt required for the remaining bits of that wordline. In the rough programming phase, the bits of core cells are then programmed from a starting point that is relative to (e. g.

US Patent:

7251158, Jul 31, 2007

Filed:

Jun 10, 2004

Appl. No.:

10/864947

Inventors:

Ed Hsia - Saratoga CA, US
Darlene Hamilton - San Jose CA, US
Fatima Bathul - Cupertino CA, US
Masato Horiike - Sunnyvale CA, US

Assignee:

Spansion LLC - Sunnyvale CA

International Classification:

G11C 11/34

US Classification:

36518503, 36518529, 3651853

Abstract:

Methods of erasing a sector of multi-level flash memory cells (MLB) having three or more data states to a single data state are provided. The present invention employs an interactive sector erase algorithm that repeatedly erases, verifies, soft programs, and programs the sector in two or more erase phases to achieve highly compact data state distributions. In one example, the algorithm essentially erases all the MLB cells of the sector to an intermediate state and corresponding threshold voltage value using interactive erasing, soft programming and programming pulses in a first phase. Then in a second phase, the algorithm further erases all the MLB cells of the sector using additional interactive erasing and soft programming pulses until a final data state is achieved corresponding to a desired final threshold voltage value of the cells. Optionally, the algorithm may include one or more additional phases of similar operations that successively bring the memory cells of the sector to a compacted common erased state in preparation for subsequent programming operations. In one aspect of the method, the actual threshold values and/or data states chosen for these phases may be predetermined and input to the memory device by the user.

US Patent:

20060062054, Mar 23, 2006

Filed:

Sep 22, 2004

Appl. No.:

10/946809

Inventors:

Darlene Hamilton - San Jose CA, US
Fatima Bathul - Cupertino CA, US
Masato Horiike - Sunnyvale CA, US
Eugen Gershon - San Jose CA, US
Michael Buskirk - Saratoga CA, US

International Classification:

G11C 7/06
G11C 11/34

US Classification:

365189070, 365185210, 365185200

Abstract:

The present invention pertains to a technique for determining the level of a bit in a dual sided ONO flash memory cell where each of the bits of the dual sided ONO flash memory cell can be programmed to multiple levels. One or more aspects of the present invention take into consideration the affect that the level of charge on one bit can have on the other bit, otherwise known as complimentary bit disturb. A metric known as transconductance is utilized in making the bit level determination to provide a greater degree of resolution and accuracy. In this manner, determining the bit level in accordance with one or more aspects of the present invention mitigates false or erroneous reads.