Masato H Takagi
age ~49
from San Jose, CA
- Also known as:
-
- Masato Henry Takagi
- Nasato Takagi
- Musato Takagi
- Takagi Masato
- Phone and address:
- 4782 Blue Ridge Dr, San Jose, CA 95129
Masato Takagi Phones & Addresses
- 4782 Blue Ridge Dr, San Jose, CA 95129
- 1550 Technology Dr, San Jose, CA 95110
- 1550 Technology Dr UNIT 3124, San Jose, CA 95110
- 2537 Fallingtree Dr, San Jose, CA 95131
- San Francisco, CA
- 1235 Wildwood Ave, Sunnyvale, CA 94089
- Santa Clara, CA
- 1550 Technology Dr UNIT 3063, San Jose, CA 95110
Work
-
Company:Lsi corporation - San Jose, CAMay 2011
-
Position:Staff asic design engineer
Education
-
School / High School:McMaster University1999
-
Specialities:B.Eng. in Computer Engineering
Skills
Asic • Fpga • Debugging • Simulations • Logic Design • Integrated Circuit Design • Soc • Rtl Design • Verilog • Static Timing Analysis • Functional Verification • Systemverilog • Eda • Ic • Vlsi • Dft • Tcl • Primetime • Hardware Architecture • Field Programmable Gate Arrays • Application Specific Integrated Circuits
Languages
English • Japanese
Industries
Semiconductors
Resumes
Principal Ic Design Engineer
view sourceLocation:
San Francisco, CA
Industry:
Semiconductors
Work:
Broadcom
Principal Ic Design Engineer
Huawei Technologies Oct 2014 - Aug 2015
Staff Fpga Design Engineer
Lsi Corporation May 2011 - May 2014
Staff Asic Design Engineer
Panasonic May 2001 - Jan 2011
Senior Asic Design Engineer
Nokia Feb 2001 - May 2001
Asic Design Engineer
Principal Ic Design Engineer
Huawei Technologies Oct 2014 - Aug 2015
Staff Fpga Design Engineer
Lsi Corporation May 2011 - May 2014
Staff Asic Design Engineer
Panasonic May 2001 - Jan 2011
Senior Asic Design Engineer
Nokia Feb 2001 - May 2001
Asic Design Engineer
Education:
Mcmaster University 1994 - 1999
Bachelor of Engineering, Bachelors, Computer Engineering
Bachelor of Engineering, Bachelors, Computer Engineering
Skills:
Asic
Fpga
Debugging
Simulations
Logic Design
Integrated Circuit Design
Soc
Rtl Design
Verilog
Static Timing Analysis
Functional Verification
Systemverilog
Eda
Ic
Vlsi
Dft
Tcl
Primetime
Hardware Architecture
Field Programmable Gate Arrays
Application Specific Integrated Circuits
Fpga
Debugging
Simulations
Logic Design
Integrated Circuit Design
Soc
Rtl Design
Verilog
Static Timing Analysis
Functional Verification
Systemverilog
Eda
Ic
Vlsi
Dft
Tcl
Primetime
Hardware Architecture
Field Programmable Gate Arrays
Application Specific Integrated Circuits
Languages:
English
Japanese
Japanese
Masato Takagi San Jose, CA
view sourceWork:
LSI Corporation
San Jose, CA
May 2011 to May 2014
Staff ASIC Design Engineer Panasonic Semiconductor
Cupertino, CA
May 2001 to Jan 2011
Senior ASIC Design Engineer Nokia Corporation
Burlington, MA
Feb 2001 to May 2001
ASIC Design Engineer Quarry Technologies
Burlington, MA
Sep 1999 to Jan 2001
ASIC Verification Engineer
San Jose, CA
May 2011 to May 2014
Staff ASIC Design Engineer Panasonic Semiconductor
Cupertino, CA
May 2001 to Jan 2011
Senior ASIC Design Engineer Nokia Corporation
Burlington, MA
Feb 2001 to May 2001
ASIC Design Engineer Quarry Technologies
Burlington, MA
Sep 1999 to Jan 2001
ASIC Verification Engineer
Education:
McMaster University
1999
B.Eng. in Computer Engineering
1999
B.Eng. in Computer Engineering
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