Matthew E Chraft

US Patent:

7307433, Dec 11, 2007

Filed:

Apr 21, 2004

Appl. No.:

10/828755

Inventors:

Charles A. Miller - Fremont CA, US
Matthew E. Chraft - Copperopolis CA, US
Roy J. Henson - Pleasanton CA, US

Assignee:

FormFactor, Inc. - Livermore CA

International Classification:

G01R 31/02
G01R 31/06

US Classification:

324754, 324765

Abstract:

A probe card for a wafer test system is provided with a number of on board features enabling fan out of a test system controller channel to test multiple DUTs on a wafer, while limiting undesirable effects of fan out on test results. On board features of the probe card include one or more of the following: (a) DUT signal isolation provided by placing resistors in series with each DUT input to isolate failed DUTs; (b) DUT power isolation provided by switches, current limiters, or regulators in series with each DUT power pin to isolate the power supply from failed DUTs; (c) self test provided using an on board micro-controller or FPGA; (d) stacked daughter cards provided as part of the probe card to accommodate the additional on board test circuitry; and (e) use of a interface bus between a base PCB and daughter cards of the probe card, or the test system controller to minimize the number of interface wires between the base PCB and daughter cards or between the base PCB and the test system controller.

US Patent:

7852094, Dec 14, 2010

Filed:

Dec 6, 2006

Appl. No.:

11/567705

Inventors:

Matthew E. Chraft - Copperopolis CA, US
Benjamin N. Eldridge - Danville CA, US
Roy J. Henson - Pleasanton CA, US
A. Nicholas Sporck - Saratoga CA, US

Assignee:

FormFactor, Inc. - Livermore CA

International Classification:

G01R 31/02

US Classification:

324754, 324765, 3241581

Abstract:

Probes in a plurality of DUT probe groups can be connected in parallel to a single tester channel. In one aspect, digital potentiometers can be used to effectively switch the tester channel from a probe in one DUT probe group to a probe in another DUT probe group. In another aspect, switches in parallel with a resistor can accomplish such switching. In yet another aspect, a chip select terminal on each DUT can be used to effectively connect and disconnect internal DUT circuitry to the tester channel. Multiple DUT probe groups so connected can be used to create different patterns of DUT probe groups for testing different patterns of DUTs and thus facilitate sharing tester channels.

US Patent:

8581610, Nov 12, 2013

Filed:

Jun 13, 2006

Appl. No.:

11/452784

Inventors:

Charles A Miller - Fremont CA, US
Matthew E Chraft - Copperopolis CA, US
Roy J Henson - Pleasanton CA, US

International Classification:

G01R 31/20

US Classification:

32475401, 324500, 32475501, 32475603, 32476203, 716136

Abstract:

A method is provided for design and programming of a probe card with an on-board programmable controller in a wafer test system. Consideration of introduction of the programmable controller is included in a CAD wafer layout and probe card design process. The CAD design is further loaded into the programmable controller, such as an FPGA to program it: (1) to control direction of signals to particular ICs, even during the test process (2) to generate test vector signals to provide to the ICs, and (3) to receive test signals and process test results from the received signals. In some embodiments, burn-in only testing is provided to limit test system circuitry needed so that with a programmable controller on the probe card, text equipment external to the probe card can be eliminated or significantly reduced from conventional test equipment.

US Patent:

20040046579, Mar 11, 2004

Filed:

May 5, 2003

Appl. No.:

10/430628

Inventors:

Matthew Chraft - Atwater CA, US
Roy Henson - Pleasanton CA, US
Charles Miller - Fremont CA, US
Chih-Chiang Tseng - Dublin CA, US

Assignee:

FormFactor, Inc.

International Classification:

G01R031/02

US Classification:

324/754000

Abstract:

A probe system for providing signal paths between an integrated circuit (IC) tester and input/output, power and ground pads on the surfaces of ICs to be tested includes a probe board assembly, a flex cable and a set of probes arranged to contact the IC's I/O pads. The probe board assembly includes one or more rigid substrate layers with traces and vias formed on or within the substrate layers providing relatively low bandwidth signal paths linking the tester to probes accessing some of the IC's pads. The flex cable provides relatively high bandwidth signal paths linking the tester to probes accessing others of the IC's pads. A flex strip may alternatively be disposed behind a substrate with probes.

US Patent:

20060214679, Sep 28, 2006

Filed:

Mar 28, 2005

Appl. No.:

11/091069

Inventors:

Roy Henson - Pleasanton CA, US
Matthew Chraft - Copperopolis CA, US

Assignee:

FormFactor, Inc. - Livermore CA

International Classification:

G01R 31/26

US Classification:

324765000

Abstract:

A diagnostic interface on a wafer probe card is provided to enable monitoring of test signals provided between the test system controller and one or more DUTs on a wafer during wafer testing. To prevent distortion of test signals on the channel lines, in one embodiment buffers are provided on the probe card as part of the diagnostic interface connecting to the channels. In another embodiment, an interface adapter pod is provided that connects to the diagnostic interface on the probe card to process the test results and provide the results to a user interface such as a personal computer.

US Patent:

20080100320, May 1, 2008

Filed:

Dec 11, 2007

Appl. No.:

12/001281

Inventors:

Charles Miller - Fremont CA, US
Matthew Chraft - Copperopolis CA, US
Roy Henson - Pleasanton CA, US

International Classification:

G01R 31/26

US Classification:

324754000

Abstract:

A probe card for a wafer test system is provided with a number of on board features enabling fan out of a test system controller channel to test multiple DUTs on a wafer, while limiting undesirable effects of fan out on test results. On board features of the probe card include one or more of the following: (a) DUT signal isolation provided by placing resistors in series with each DUT input to isolate failed DUTs; (b) DUT power isolation provided by switches, current limiters, or regulators in series with each DUT power pin to isolate the power supply from failed DUTs; (c) self test provided using an on board micro-controller or FPGA; (d) stacked daughter cards provided as part of the probe card to accommodate the additional on board test circuitry; and (e) use of a interface bus between a base PCB and daughter cards of the probe card, or the test system controller to minimize the number of interface wires between the base PCB and daughter cards or between the base PCB and the test system controller.