Matthew J Reilly

US Patent:

7660270, Feb 9, 2010

Filed:

Nov 8, 2006

Appl. No.:

11/594416

Inventors:

Judson S. Leonard - Newton MA, US
Matthew H. Reilly - Stow MA, US
Lawrence C. Stewart - Wayland MA, US
Washington Taylor - Cambridge MA, US

Assignee:

SiCortex, Inc. - Maynard MA

International Classification:

H04L 12/28

US Classification:

370255, 370254, 370203

Abstract:

Computer systems and methods using efficient module and backplane tiling to interconnect computer nodes via a Kautz-like digraph. A multinode computing system includes a large plurality of computing nodes interconnected via a Kautz topology having order O, diameter n, and degree k. The order equals (k+1)k. The interconnections from a node x to a node y in the topology satisfy the relationship y=(−x*k−j) mod O, where 1≦j≦k, and the computing nodes are arranged onto a plurality of modules. Each module has an equal plurality of computing nodes on it. A majority of the inter-node connections are contained on the plurality of modules and a minority of the inter-node connections are inter-module connections. Inter-module connections are routed among modules in parallel on an inter-module connection plane.

US Patent:

7751344, Jul 6, 2010

Filed:

Nov 8, 2006

Appl. No.:

11/594423

Inventors:

Judson S. Leonard - Newton MA, US
Matthew H. Reilly - Stow MA, US
Lawrence C. Stewart - Wayland MA, US
Washington Taylor - Cambridge MA, US

Assignee:

SiCortex, Inc. - Maynard MA

International Classification:

H04L 12/28

US Classification:

370255, 370230, 370231, 370235, 370236, 370237, 370254, 709220, 709221, 709222, 709225, 709226, 709227, 709228, 709229

Abstract:

Computer system and method using a Kautz-like digraph to interconnect computer nodes and having control back channel between nodes. A multinode computing system includes a large plurality of computing nodes interconnected via a Kautz topology having order O, diameter n, and degree k. The order equals (k+1)k; The data interconnections from a node x to a node y in the topology satisfy the relationship y=(−x*k−j) mod O, where 1≦j≦k; and each x,y pair includes a unidirectional control link from node y to node x to convey flow control and error information from a receiving node y to a transmitting node x.

US Patent:

7773618, Aug 10, 2010

Filed:

Nov 8, 2006

Appl. No.:

11/594426

Inventors:

Judson S. Leonard - Newton MA, US
Matthew H. Reilly - Stow MA, US
Nitin Godiwala - Boylston MA, US

Assignee:

SiCortex, Inc. - Maynard MA

International Classification:

H04L 12/28
H04L 12/56

US Classification:

370409, 370396, 370400

Abstract:

Systems and methods for preventing deadlock in richly-connected multiprocessor computer system using dynamic assignment of virtual channels. Deadlock is prevented in a multiprocessor computer system having a large plurality of processing nodes interconnected by a defined interconnection topology. Each link in the interconnection topology is associated with a set of virtual channels. Each virtual channel has corresponding communication buffers to store communication data and each virtual channel has an associated virtual channel identifier. Each communication between a source processing node and a target processing node is assigned an initial virtual channel to convey the communication from the source processing node. At an intermediate processing node, a different virtual channel is assigned to convey the communication toward the target processing node, in accordance with pre-defined rules to avoid a cycle of dependency of communication buffer resources.

US Patent:

20070168620, Jul 19, 2007

Filed:

Jan 19, 2006

Appl. No.:

11/335421

Inventors:

Judson Leonard - Newton MA, US
Matthew Reilly - Stow MA, US

International Classification:

G06F 13/28

US Classification:

711141000

Abstract:

Systems and methods for cache coherency in multi-processor systems. A cache coherency system is used in a multi-processor computer system having a physical memory system in communication with the processors via a communication medium. A processor-side cache memory subsystem is associated with each processor of the multi-processor computer system. The cache coherency system includes a cache tag memory structure having a number of entries substantially equal to the defined number of entries for each processor-side cache memory. Each entry of the cache tag memory structure has at least one field corresponding to each processor-side cache memory subsystem.