Matthew Christopher Reilly

US Patent:

6493741, Dec 10, 2002

Filed:

Oct 1, 1999

Appl. No.:

09/411194

Inventors:

Joel S. Emer - Acton MA
Rebecca L. Stamm - Palo Alto CA
Bruce E. Edwards - Belmont MA
Matthew H. Reilly - Stow MA
Craig B. Zilles - Middleton WI
Tryggve Fossum - Northborough MA
Christopher F. Joerg - Watertown MA

Assignee:

Compaq Information Technologies Group, L.P. - Houston TX

International Classification:

G06F 948

US Classification:

709107, 709102, 710200, 711151, 712228

Abstract:

Execution of a programs instructions in a simultaneous multithreaded processor is halted while the program is waiting for one or more events to occur by first arming an event monitor upon an arm instruction, that is, identifying to the event monitor one or more events to be monitored, such as a modification to a value or state of an identified memory location or group of locations, and setting a watch flag to indicate enable the event monitor. Upon execution of a quiesce request instruction, the program quiesces if the watch flag is set, and a timer is started. Upon observation by the event monitor of an identified event, or upon expiration of the timer, the watch flag is cleared and execution of the program resumes.

US Patent:

6675192, Jan 6, 2004

Filed:

Nov 11, 2002

Appl. No.:

10/293975

Inventors:

Joel S. Emer - Acton MA
Rebecca L. Stamm - Palo Alto CA
Bruce E. Edwards - Belmont MA
Matthew H. Reilly - Stow MA
Craig B. Zilles - Middleton WI
Tryggve Fossum - Northborough MA
Christopher F. Joerg - Watertown MA

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 948

US Classification:

709107, 709102, 710 18, 711156, 712229

Abstract:

Execution of a programs instructions in a simultaneous multithreaded processor is halted while the program is waiting for one or more events to occur by first arming an event monitor upon an arm instruction, that is, identifying to the event monitor one or more events to be monitored, such as a modification to a value or state of an identified memory location or group of locations, and setting a watch flag to indicate enable the event monitor. Upon execution of a quiesce request instruction, the program quiesces if the watch flag is set, and a timer is started. Upon observation by the event monitor of an identified event, or upon expiration of the timer, the watch flag is cleared and execution of the program resumes.

US Patent:

6925552, Aug 2, 2005

Filed:

Jun 19, 2001

Appl. No.:

09/884675

Inventors:

Matthew H. Reilly - Stow MA, US
Matthew C. Mattina - Hudson MA, US
Shane L. Bell - Shrewsbury MA, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F009/00

US Classification:

712244

Abstract:

An exception handler for a processor is split into two functional units to permit exceptions to be classified into two categories. The first category of exceptions includes performance critical excepted instructions, while the second category includes non-performance critical excepted instructions. The performance critical exceptions are routed to a speculative exception handler, which resolves the exceptions speculatively, even though the excepted instruction may lie in a speculative path of the program flow. The non-performance critical exceptions are routed to a non-speculative exception handler that only resolves exceptions when the excepted instruction is certain to execute in an actual path of the program flow.

US Patent:

7660270, Feb 9, 2010

Filed:

Nov 8, 2006

Appl. No.:

11/594416

Inventors:

Judson S. Leonard - Newton MA, US
Matthew H. Reilly - Stow MA, US
Lawrence C. Stewart - Wayland MA, US
Washington Taylor - Cambridge MA, US

Assignee:

SiCortex, Inc. - Maynard MA

International Classification:

H04L 12/28

US Classification:

370255, 370254, 370203

Abstract:

Computer systems and methods using efficient module and backplane tiling to interconnect computer nodes via a Kautz-like digraph. A multinode computing system includes a large plurality of computing nodes interconnected via a Kautz topology having order O, diameter n, and degree k. The order equals (k+1)k. The interconnections from a node x to a node y in the topology satisfy the relationship y=(−x*k−j) mod O, where 1≦j≦k, and the computing nodes are arranged onto a plurality of modules. Each module has an equal plurality of computing nodes on it. A majority of the inter-node connections are contained on the plurality of modules and a minority of the inter-node connections are inter-module connections. Inter-module connections are routed among modules in parallel on an inter-module connection plane.

US Patent:

7751344, Jul 6, 2010

Filed:

Nov 8, 2006

Appl. No.:

11/594423

Inventors:

Judson S. Leonard - Newton MA, US
Matthew H. Reilly - Stow MA, US
Lawrence C. Stewart - Wayland MA, US
Washington Taylor - Cambridge MA, US

Assignee:

SiCortex, Inc. - Maynard MA

International Classification:

H04L 12/28

US Classification:

370255, 370230, 370231, 370235, 370236, 370237, 370254, 709220, 709221, 709222, 709225, 709226, 709227, 709228, 709229

Abstract:

Computer system and method using a Kautz-like digraph to interconnect computer nodes and having control back channel between nodes. A multinode computing system includes a large plurality of computing nodes interconnected via a Kautz topology having order O, diameter n, and degree k. The order equals (k+1)k; The data interconnections from a node x to a node y in the topology satisfy the relationship y=(−x*k−j) mod O, where 1≦j≦k; and each x,y pair includes a unidirectional control link from node y to node x to convey flow control and error information from a receiving node y to a transmitting node x.

US Patent:

7773616, Aug 10, 2010

Filed:

Nov 8, 2006

Appl. No.:

11/594405

Inventors:

Matthew H. Reilly - Stow MA, US
Nitin Godiwala - Boylston MA, US
Judson S. Leonard - Newton MA, US

Assignee:

SiCortex, Inc. - Maynard MA

International Classification:

H04L 12/28
H04L 12/56

US Classification:

370409, 370400, 370401, 370414, 370396, 370397

Abstract:

Systems and methods for communicating on a richly-connected multiprocessor computer system using a pool of buffers for dynamic association with a virtual channel. Packets are communicated in a multiprocessor computer system having a large plurality of processing nodes interconnected by a defined interconnection topology, in which a communication from a source processing node to a target processing node may pass through one or more intermediate nodes en route to the target processing node. A set of virtual channels is associated for each link in the interconnection topology. A first subset of buffers is dedicated for fixed correspondence to virtual channel identifiers, and a second subset of buffers is dedicated for dynamic allocation and assignment to virtual channels.

US Patent:

7773618, Aug 10, 2010

Filed:

Nov 8, 2006

Appl. No.:

11/594426

Inventors:

Judson S. Leonard - Newton MA, US
Matthew H. Reilly - Stow MA, US
Nitin Godiwala - Boylston MA, US

Assignee:

SiCortex, Inc. - Maynard MA

International Classification:

H04L 12/28
H04L 12/56

US Classification:

370409, 370396, 370400

Abstract:

Systems and methods for preventing deadlock in richly-connected multiprocessor computer system using dynamic assignment of virtual channels. Deadlock is prevented in a multiprocessor computer system having a large plurality of processing nodes interconnected by a defined interconnection topology. Each link in the interconnection topology is associated with a set of virtual channels. Each virtual channel has corresponding communication buffers to store communication data and each virtual channel has an associated virtual channel identifier. Each communication between a source processing node and a target processing node is assigned an initial virtual channel to convey the communication from the source processing node. At an intermediate processing node, a different virtual channel is assigned to convey the communication toward the target processing node, in accordance with pre-defined rules to avoid a cycle of dependency of communication buffer resources.

US Patent:

20040073905, Apr 15, 2004

Filed:

Oct 7, 2003

Appl. No.:

10/680375

Inventors:

Joel Emer - Acton MA, US
Rebecca Stamm - Palo Alto CA, US
Bruce Edwards - Belmont MA, US
Matthew Reilly - Stow MA, US
Craig Zilles - Middleton WI, US
Tryggve Fossum - Northborough MA, US
Christopher Joerg - Wattertown MA, US
James Hicks - Newton MA, US

International Classification:

G06F009/00

US Classification:

718/101000

Abstract:

Execution of a program's instructions in a simultaneous multithreaded processor is halted while the program is waiting for one or more events to occur by first arming an event monitor upon an arm instruction, that is, identifying to the event monitor one or more events to be monitored, such as a modification to a value or state of an identified memory location or group of locations, and setting a watch flag to indicate enable the event monitor. Upon execution of a quiesce request instruction, the program quiesces if the watch flag is set, and a timer is started. Upon observation by the event monitor of an identified event, or upon expiration of the timer, the watch flag is cleared and execution of the program resumes.