Matthew W Webb

US Patent:

7208981, Apr 24, 2007

Filed:

Apr 20, 2005

Appl. No.:

10/907904

Inventors:

Ramsin M. Ziazadeh - San Jose CA, US
Vijaya Ceekala - San Jose CA, US
Matthew James Webb - Woodland Hills CA, US
James B. Wieser - Pleasanton CA, US

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

H03K 5/22

US Classification:

327 65, 327 77, 327 89, 714733

Abstract:

A circuit and method are provided for performing built-in test of output signal magnitudes of integrated differential signal generator circuitry. In accordance with one embodiment, first upper and lower reference voltages and second upper and lower reference voltages are received via a plurality of reference electrodes, wherein: a difference between the first and upper and lower reference voltages comprises a first difference magnitude; a difference between the second upper and lower reference voltages comprises a second difference magnitude; and the first difference magnitude is greater than the second difference magnitude. Test signal generator circuitry provides a plurality of binary signals with respective successions of opposing signal states. Differential signal generator circuitry, coupled to the test signal generator circuitry and responsive to the plurality of binary signals, provides a plurality of differential signals having respective magnitudes related to the respective successions of opposing binary signal states. Signal comparison circuitry, coupled to the plurality of reference electrodes and the differential signal generator circuitry, and responsive to the first and second upper and lower reference signals and the plurality of differential signals, provides a plurality of test signals with respective test signal states indicative of whether respective ones of the differential signal magnitudes are within a range defined as being less than the first difference magnitude and greater than the second difference magnitude.

US Patent:

20190207868, Jul 4, 2019

Filed:

Feb 15, 2019

Appl. No.:

16/276979

Inventors:

- Santa Clara CA, US
Daniel Christian BIEDERMAN - Saratoga CA, US
Matthew James WEBB - Woodland Hills CA, US
Wing CHEUNG - Fremont CA, US
Jose NIELL - Franklin MA, US
Robert HATHAWAY - Sunnyvale CA, US

International Classification:

H04L 12/927
H04L 12/851
H04L 12/721
H04L 12/24

Abstract:

A compute device can access local or remote accelerator devices for use in processing a received packet. The received packet can be processed by any combination of local accelerator devices and remote accelerator devices. In some cases, the received packet can be encapsulated in an encapsulating packet and sent to a remote accelerator device for processing. The encapsulating packet can indicate a priority level for processing the received packet and its associated processing task. The priority level can override a priority level that would otherwise be assigned to the received packet and its associated processing task. The remote accelerator device can specify a fullness of an input queue to the compute device. Other information can be conveyed by packets transmitted between and among compute devices and remote accelerator devices to assist in determining an accelerator to use or other uses.