Maulik Joshi

US Patent:

20100169065, Jul 1, 2010

Filed:

Dec 31, 2008

Appl. No.:

12/346956

Inventors:

Maulik Joshi - Sunnyvale CA, US
Ivan Herrera Mejia - Folsom CA, US
Joshua D. Louie - Roseville CA, US

International Classification:

G06F 17/00

US Classification:

703 16

Abstract:

In general, in one aspect, the disclosure describes creation of a randomization list that includes only a subset of the logic states of an integrated circuit (IC). The subset being selectable by signal so as to define logic states that can be randomized for specific events. The randomization list is during simulation to randomize the logic states defined therein to simulate a specific event occurring during operation of the IC. For example, the randomization list may include those signals that can be randomized upon exiting from a powered down state (e.g., deep power down, C6). The signals that can be randomized may be defined by excluding the signals that cannot be randomized (those still receiving power in the C6 mode). The contents of registers of the IC can be confirmed after the randomization and exit from the C6 mode.