Max R Brown

US Patent:

39626830, Jun 8, 1976

Filed:

Sep 4, 1973

Appl. No.:

5/394361

Inventors:

Max Brown - Houston TX
Gary Boone - Houston TX

International Classification:

G06f 900

US Classification:

3401725

Abstract:

A synchronous computing system includes a central processor unit interconnected with external memory units. The processor is integrated monolithically on a single chip and includes a plurality of data registers, a parallel arithmetic logic unit and an instruction register interconnected by a common parallel buss. A control section of the processor synchronizes internal operation of the processor and also system operation, and includes a plurality of programmable logic arrays to provide a versatile method of accommodating different instruction sets, sequences of operation, and instruction cycle duration. The arrays reduce the number of interconnects required and increases utilization of semiconductor material for forming active devices. This is a continuation of application Ser. No. 176,665, filed Aug.