Max N Yoder

US Patent:

53110552, May 10, 1994

Filed:

Nov 22, 1991

Appl. No.:

7/796553

Inventors:

Alvin M. Goodman - Arlington VA
Max N. Yoder - Falls Church VA

Assignee:

The United States of America as represented by the Secretary of the Navy - Washington DC

International Classification:

H01L 2972
C30B 2300

US Classification:

257593

Abstract:

Both homojunction and heterojunction bipolar transistor structures are fabricated in unique trenched configurations so as to better utilize their surface areas by employing both the vertical and horizontal portions of their base regions with equal effectiveness. An important advantage of the unique trenched configurations is that the base region of each trenched structure is of precisely the same thickness throughout--both vertical and horizontal portions. Consequently, the transit time for charge carriers to diffuse across the base region and the base transport factor are uniform because of the uniform base thickness. Moreover, the parasitic capacitance region of each trenched structure beneath base metallization contacts is only a small portion of the entire base-collector junction region. Accordingly, the RC time constant of each trenched structure is very low and the high frequency response gain of the heterojunction trenched bipolar transistor structure is an order of magnitude higher than its conventional heterojunction bipolar transistor counterpart.

US Patent:

43449808, Aug 17, 1982

Filed:

Mar 25, 1981

Appl. No.:

6/247423

Inventors:

Max N. Yoder - Falls Church VA

Assignee:

The United States of America as represented by the Secretary of the Navy - Washington DC

International Classification:

H01L 2122
H01L 21265

US Classification:

427 38

Abstract:

A method for fabricating superior ohmic contacts in a III-V semiconductor wafer by virtue of double donor (or double acceptor) impurity complex formation. A typical III-V, e. g. , GaAs, semiconductor device is fabricated by depositing a thin Si. sub. 3 N. sub. 4 layer and then regions are opened, by photoresist methods, upon which ohmic contacts are to be made. New resist is applied over the wafer and the ohmic contact regions are again opened. Si ions are now implanted to form the active channel and the drain and source regions (in an FET device). The resist layer is removed, a layer of Ge is laid down and a layer of Se over the Ge. The Ge layer is coated with a layer of SiO. sub. 2, Si. sub. 3 N. sub. 4 or a mixture of both, and annealed, causing the Ge and Se to diffuse rapidly into the Si ion implant region. The SiO. sub. 2, Si. sub. 3 N. sub. 4 and excess surface Ge and Se is now removed.

US Patent:

43284981, May 4, 1982

Filed:

May 21, 1970

Appl. No.:

5/048590

Inventors:

Max N. Yoder - Washington DC

Assignee:

The United States of America as represented by the Secretary of the Navy - Washington DC

International Classification:

G01S 374
H01Q 326

US Classification:

343100SA

Abstract:

A spin stabilized, earth orbitting satellite having a phased array antenna capable of radiating a plurality of steered electromagnetic beams to predetermined earth locations. The antenna array extends around the satellite and is made up of individual elements which are energized through semiconductor diode devices by electron beams. The electron beams are controlled by fields having the same frequency as the spin frequency of the satellite.

US Patent:

H4111, Jan 5, 1988

Filed:

Aug 28, 1985

Appl. No.:

6/770166

Inventors:

Max N. Yoder - Falls Church VA

Assignee:

United States of America - Washington DC

International Classification:

H01L 2980
H01L 29161
H01L 29167

US Classification:

357 22

Abstract:

A Field Effect Transistor (FET) capable of withstanding increased positive gate biasing with respect to the source contact without incurring the penalty of drawing excessive gate current, comprising a semi-insulating substrate layer; an active channel layer of doped n-type semi-conductor material disposed on the substrate layer; a first heteroepitaxial semi-insulating layer of a semi-insulating material having a bandgap greater than the bandgap of the active channel layer material disposed on said active channel layer. The first heteroepitaxial layer has a top surface, a designated first region, a designated second region, and a designated middle section disposed therebetween wherein the first region and the second region of the first heteroepitaxial layer are implanted with activated donor impurities to form its source and drain regions. The device is also provided with conventional source, drain and gate contacts. In a preferred embodiment, a heavily donor doped Gallium arsenide heteroepitaxial layer is disposed between the source contact and the first heteroepitaxial layer and between the drain contact and the first heteroepitaxial layer.

US Patent:

53269926, Jul 5, 1994

Filed:

Jul 29, 1992

Appl. No.:

7/921151

Inventors:

Max N. Yoder - Falls Church VA

Assignee:

The United States of America as represented by the Secretary of the Navy - Washington DC

International Classification:

H01L 29161
H01L 29205
H01L 29225

US Classification:

257 77

Abstract:

A heterojunction bipolar transistor (HBT) structure is configured so that the heterojunction between hexagonal and cubic materials is electrically active. A first embodiment of the HBT structure comprises both hexagonal and cubic silicon carbide (SiC). The emitter region is fabricated from the higher bandgap hexagonal SiC appropriately doped. The base and collector regions are grown using the lower bandgap cubic SiC. A second embodiment of the HBT structure comprises both a solid solution of SiC material such as an alloy of silicon carbon aluminum nitrogen (SiCAlN) grown upon a substrate of hexagonal SiC. The emitter region can be placed either on the top or bottom of the second embodiment of the HBT structure. Also, the bandgap between the emitter and base regions of the second embodiment can be varied by controlling the mole fraction ratio between the constituent parts of the SiCAlN, i. e. , between the SiC and the AlN.

US Patent:

H3689, Nov 3, 1987

Filed:

Sep 16, 1980

Appl. No.:

6/187672

Inventors:

Max N. Yoder - Falls Church VA

Assignee:

The United States of America as represented by the Secretary of the Navy - Washington DC

International Classification:

H01L 2980
H01L 21265

US Classification:

357 22

Abstract:

A method of improving field-effect transistors, and the product thereof, wherein the resistivity of the upper layer of the source-gate channel region of a GaAs field-effect transistor (FET) may be selectively raised is disclosed. Impurity ions are implanted in the source-gate channel region followed by a much shallower implantation of boron in the same region. The boron ion concentration should exceed the N+ impurity ion concentration by a factor of 2 or more.

US Patent:

47104783, Dec 1, 1987

Filed:

May 20, 1985

Appl. No.:

6/736051

Inventors:

Max N. Yoder - Falls Church VA
George B. Wright - McLean VA

Assignee:

United States of America as represented by the Secretary of the Navy - Washington DC

International Classification:

H01L 21203

US Classification:

437 40

Abstract:

The present invention relates to complementary logic field effect transistors having high electron and hole mobility and above to maintain transistor action at cryogenic temperatures. In one embodiment germanium material is deposited upon a gallium arsenide substrate and high hole concentration areas and high electron concentration areas are created in the germanium layer. In another embodiment a germanium substrate is provided and a gallium arsenide layer is grown upon the germanium substrate with appropriate high hole concentration areas and high electron concentration areas being created within the gallium arsenide.

US Patent:

46718451, Jun 9, 1987

Filed:

Mar 22, 1985

Appl. No.:

6/714779

Inventors:

Max N. Yoder - Falls Church VA

Assignee:

The United States of America as represented by the Secretary of the Navy - Washington DC

International Classification:

C30B 3122
H01L 2124
C23C 1400

US Classification:

156610

Abstract:

The present invention relates to the production of a stable insulator of a germanium and a device produced thereby. A germanium substrate is provided with a layer of silicon nitride deposited on one of the outer surfaces. Ionized nitrogen is implanted by an ion beam into the silicon nitride layer. An electric field is applied across the substrate and layer. In one embodiment the substrate and layer are annealed while maintaining the electric field, the electric field is removed, and a second annealing step grows the germanium nitride insulator layer subcutaneously. In another embodiment the subcutaneous germanium nitride insulator layer is grown during a single annealing step by continued application of the electric field to the substrate and the layer.