Meng D Lee

US Patent:

20030079210, Apr 24, 2003

Filed:

Oct 19, 2001

Appl. No.:

09/982020

Inventors:

Peter Markstein - Woodside CA, US
Meng Lee - Cupertino CA, US

International Classification:

G06F009/45

US Classification:

717/152000, 717/146000

Abstract:

A compiler includes a real register allocation stage, an optimization stage and a final code stage. The real register allocation stage is configured to generate intermediate code from a basic block of source code. Physical registers, instead of virtual registers, are allocated to operands from the generated intermediate code, and the operands are stored in the physical registers. Then, the intermediate code is optimized, and machine readable code is generated from the intermediated code using the optimized registers in the final code stage. By allocating physical registers in the front-end of the compiler, instead of just prior to generating the machine-readable code, compiling time and memory needed for compiling source code is reduced.

US Patent:

20230063808, Mar 2, 2023

Filed:

Sep 2, 2021

Appl. No.:

17/465596

Inventors:

- Cupertino CA, US
Meng Chi Lee - Los Altos CA, US

International Classification:

H05K 1/02
H01L 23/498
H05K 1/14
H05K 3/00
H05K 3/42
H01L 21/48

Abstract:

A coaxial interposer may shield certain signals (e.g., noisy signals, high speed signals, radio frequency (RF) signals) transmitted through an electronic device. The coaxial interposer may include a coaxial via that includes an outer barrel of non-conductive material and an inner barrel of non-conductive material separated by a conductive barrel. Further, the outer barrel of non-conductive material may be enclosed by an outer metal coating. The coaxial via serves to internally shield each signals transmitted between layers of a printed circuit board (PCB) within the electronic device.

US Patent:

20230045254, Feb 9, 2023

Filed:

Jul 6, 2022

Appl. No.:

17/858443

Inventors:

- Beijing, CN
Priyanka Nilay Thakore - Mountain View CA, US
Meng Kun Lee - Cupertino CA, US

International Classification:

G06F 11/07

Abstract:

An interface receives reported information from a system on chip (SOC), where the reported information includes: (1) hardware-reported information that is reported by a hardware functional module included in the SOC and (2) firmware-reported information that is reported by a firmware functional module included in the SOC. A processor receives one or more display settings and generates visual information based at least in part on: (1) the one or more display settings, (2) the hardware-reported information, and (3) the firmware-reported information. The visual information is displayed via a display.

US Patent:

20210098187, Apr 1, 2021

Filed:

Sep 27, 2019

Appl. No.:

16/586606

Inventors:

- Cupertino CA, US
Frank Y. Yuan - Palo Alto CA, US
Xinbo He - Santa Clara CA, US
Rajarshi Paul - Los Gatos CA, US
Meng Chi Lee - Los Altos CA, US

Assignee:

Apple Inc. - Cupertino CA

International Classification:

H01F 27/29
H02M 3/135

Abstract:

Inductors that generate a reduced spurious electric-field. One example can provide an inductor where the terminals of the inductor are located at positions that reduce the spurious electric field by determining the types of signals conveyed at the terminals of the inductor and then selecting locations for the terminals based on that determination. For example, where a dynamic differential signal is applied to the inductor, the terminals of the inductor can be positioned near a physical center of the inductor.

US Patent:

20210075068, Mar 11, 2021

Filed:

Nov 16, 2020

Appl. No.:

17/099287

Inventors:

- Cupertino CA, US
David M. DeMuro - San Jose CA, US
Hongli Dai - Los Altos CA, US
Julian Malinski - Miami Beach FL, US
Julien Marcil - Cupertino CA, US
Meng Chi Lee - Cupertino CA, US
Richard Hung Minh Dinh - Cupertino CA, US
Rishabh Bhargava - Oakland CA, US
Steven D. Sterz - Cupertino CA, US
Richard M. Mank - Cupertino CA, US
Soundararajan Manthiri - Cupertino CA, US
Vijayasekaran Boovaragavan - Cupertino CA, US

International Classification:

H01M 10/42
H01M 10/48

Abstract:

Methods and systems for detecting and compensating for expansion of rechargeable batteries over time. An expansion detector may be coupled to or positioned proximate a rechargeable battery to monitor for expansion thereof. After expansion exceeding a selected threshold is detected, the expansion detector may report the expansion to an associated processing unit. The processing unit may undertake to arrest further rechargeable battery expansion by modifying or changing one or more characteristics of charging and/or discharging circuitry coupled to the rechargeable battery. For example, the processing unit may charge the rechargeable battery at a lower rate or with reduced voltage after detecting expansion.

US Patent:

20200375033, Nov 26, 2020

Filed:

Jun 5, 2020

Appl. No.:

16/894463

Inventors:

- Cupertino CA, US
Shankar Pennathur - San Jose CA, US
Mandar Painaik - Cupertino CA, US
Lan Hoang - Los Gatos CA, US
Meng Chi Lee - Los Altos CA, US

International Classification:

H05K 1/14
H05K 3/00
H05K 3/28
H05K 1/18
H05K 3/46
H01L 23/00
H01L 25/11

Abstract:

System-in-package structures and methods of assembly are described. In an embodiment, a system-in-package includes opposing circuit boards, each including mounted components overlapping the mounted components of the opposing circuit board. A gap between the opposing circuit boards may be filled with a molding material, that additionally encapsulates the overlapping mounted components. In some embodiments, the opposing circuit boards are stacked on one another using one or more interposers that may provide mechanical or electrical connection.

US Patent:

20200144142, May 7, 2020

Filed:

Dec 5, 2019

Appl. No.:

16/704671

Inventors:

Flynn P. Carson - Redwood City CA, US
Jun Chung Hsu - Cupertino CA, US
Meng Chi Lee - Los Altos CA, US
Shatki S. Chauhan - Cupertino CA, US

International Classification:

H01L 23/28
H01L 21/56
H01L 21/78
H01L 21/48
H01L 23/00

Abstract:

Packages including substrate-less integrated components and methods of fabrication are described are described. In an embodiment, a packaging method includes attaching a ground structure to a carrier and a plurality of components face down to the carrier and laterally adjacent to the ground structure. The plurality of components are encapsulated within a molding compound, and the carrier is removed exposing a plurality of component terminals and a plurality of ground structure terminals. A plurality of packages are singulated.

US Patent:

20200066457, Feb 27, 2020

Filed:

Aug 24, 2018

Appl. No.:

16/112500

Inventors:

- Cupertino CA, US
James John Ashe - Saratoga CA, US
Gang Ning - Santa Clara CA, US
Won Seop Choi - Pleasanton CA, US
Meng Chi Lee - Los Altos CA, US
Parin Patel - San Jose CA, US
Samuel Benjamin Schaevitz - Los Gatos CA, US
Derek J. DiCarlo - San Jose CA, US

International Classification:

H01G 4/40
H01G 4/005
H01G 4/12
H01G 4/30

Abstract:

Capacitors, including multilayer ceramic capacitors, may be subject to faults and failures that create short circuits between their dielectrics. Capacitors having fuses that protect the capacitors or the electrical devices using the capacitors when such faults occur are described herein. Embodiments include the presence of monolithic and non-monolithic structures including the fuse. Embodiments also include capacitors with multiple fuses that may prevent or mitigate capacitor failure. Methods for manufacturing and using the capacitors are also described.