Micah Charles Knapp

US Patent:

6594184, Jul 15, 2003

Filed:

Sep 6, 2001

Appl. No.:

09/948180

Inventors:

Julie M. Staraitis - Ayer MA
Marc E. Lamere - Carlisle MA
Jason Eisenberg - Mountain View CA
Micah C. Knapp - Cambridge MA

Assignee:

Sun Microsystems, Inc. - Palo Alto CA

International Classification:

G11C 700

US Classification:

36518908

Abstract:

A memory array includes a plurality of memory cells logically arranged in M rows and N columns, wherein N is the number of memory cells per word of digital information and M is the number of words within the array. A plurality of N data output lines are associated with each of the N columns of the array for selectively retrieving output data from a word located at a predetermined word address in the array. Each data output line is selectively shared by each of the M memory cells within its associated column. Each of the cell output lines of the M memory cells in each of the N columns are logically OR-ed together to provide the output data retrieved by each data output line associated with each of the N columns.

US Patent:

6799308, Sep 28, 2004

Filed:

Dec 19, 2002

Appl. No.:

10/325806

Inventors:

Eileen H. You - Saratoga CA
Matthew E. Becker - Harvard MA
Thomas E. Dillinger - Chelmsford MA
Micah C. Knapp - Cambridge MA
Daniel J. Flees - San Jose CA
Peter R. OBrien - Austin TX
Chung Lau Chan - San Carlos CA

Assignee:

Sun Microsystems, Inc. - Palo Alto CA

International Classification:

G06F 1750

US Classification:

716 6, 716 4, 716 5

Abstract:

In accordance with the present invention, a method, system, computer system, and computer program product for considering clock skew in designing digital systems with latch-controlled circuits are provided. The disclosure teaches a method for determining whether logic operations can be performed within the available time and allows detailed modeling of clock skew for different domains of the integrated circuit. Taking clock skew into account for each domain, worst-case timing paths can be determined for circuits controlled by either flip-flops or latches. A design of an integrated circuit can be revised or verified using the method taught. The disclosure envisions that integrated circuits, printed circuit boards, computer systems and other components will be manufactured based upon designs developed with the method taught.

US Patent:

6862676, Mar 1, 2005

Filed:

Jan 16, 2001

Appl. No.:

09/761494

Inventors:

Micah C. Knapp - Cambridge MA, US
Poonacha P. Kongetira - Palo Alto CA, US
Marc E. Lamere - Carlisle MA, US
Julie M. Staraitis - Ayer MA, US

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G06F009/34
G06F012/06

US Classification:

712217, 712 23, 712 27, 712213, 712248, 712206, 711108, 711214

Abstract:

A superscalar processor having a content addressable memory structure that transmits a first and second output signal is presented. The superscalar processor performs out of order processing on an instruction set. From the first output signal, the dependencies between currently fetched instructions of the instruction set and previous in-flight instructions can be determined and used to generate a dependency matrix for all in-flight instructions. From the second output signal, the physical register addresses of the data required to execute an instruction, once the dependencies have been removed, may be determined.