Michael J Blake

US Patent:

6988173, Jan 17, 2006

Filed:

May 12, 2003

Appl. No.:

10/435878

Inventors:

Michael A. Blake - Wappingers Falls NY, US
Steven M. German - Wayland MA, US
Pak-kin Mak - Poughkeepsie NY, US
Adrian E. Seigler - Poughkeepsie NY, US
Gary A. Van Huben - Poughkeepsie NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/00

US Classification:

711147

Abstract:

A bus protocol is disclosed for a symmetric multiprocessing computer system consisting of a plurality of nodes, each of which contains a multitude of processors, I/O devices, main memory and a system controller comprising an integrated switch with a top level cache. The nodes are interconnected by a dual concentric ring topology. The bus protocol is used to exchange snoop requests and addresses, data, coherency information and operational status between nodes in a manner that allows partial coherency results to be passed in parallel with a snoop request and address as an operation is forwarded along each ring. Each node combines it's own coherency results with the partial coherency results it received prior to forwarding the snoop request, address and updated partial coherency results to the next node on the ring. The protocol allows each node in the system to see the final coherency results without requiring the requesting node to broadcast these results to all the other nodes in the system. The bus protocol also allows data to be returned on one of the two rings, with the ring selection determined by the relative placement of the source and destination nodes on each ring, in order to control latency and data bus utilization.

US Patent:

7069362, Jun 27, 2006

Filed:

May 12, 2003

Appl. No.:

10/436378

Inventors:

Michael A. Blake - Wappingers Falls NY, US
Pak-kin Mak - Poughkeepsie NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 13/00

US Classification:

710107, 710300, 709213

Abstract:

A dual ring topology for multiprocessing computer systems. The dual ring topology interconnects multiple building blocks (nodes) to each other, each node comprising processing elements, memory and IO devices. The topology allows for the dual rings to be temporarily transformed into a single ring structure while a node is added, repaired or replaced while the rest of the system continues to operate thereby allowing the remaining nodes in the system to remain fully connected to one another.

US Patent:

7085897, Aug 1, 2006

Filed:

May 12, 2003

Appl. No.:

10/436491

Inventors:

Michael A. Blake - Wappingers Falls NY, US
Carl B. Ford - Poughkeepsie NY, US
Pak-kin Mak - Poughkeepsie NY, US
Gary E. Strait - Poughkeepsie NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/00

US Classification:

711144

Abstract:

A modular multiprocessor computer system having a plurality of nodes each being in communication with each other via communication links. The plurality of nodes each have local memory and local cache accessible by the other nodes. The plurality of nodes each also having a cache directory, one or more processing units, and a memory coherent directory to keep track of the scope of ownership of data within the modular multiprocessing computer system. The local memory and the local cache contain configurable regions of storage, wherein memory coherency traffic on the communication links between the nodes is controlled through the use of the memory coherent directory during a data request.

US Patent:

7085898, Aug 1, 2006

Filed:

May 12, 2003

Appl. No.:

10/435776

Inventors:

Michael A. Blake - Wappingers Falls NY, US
Pak-kin Mak - Poughkeepsie NY, US
Adrian E. Seigler - Poughkeepsie NY, US
Gary A. VanHuben - Poughkeepsie NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/00
G06F 15/167
H04L 12/43

US Classification:

711147, 711146, 711141, 711168, 370460

Abstract:

An apparatus and method is disclosed to manage storage coherency in a symmetric multiprocessing environment having a plurality of nodes, each of which contain a multitude of processors, I/O adapters, main memory and a system controller comprising an integrated switch with a top level cache. The nodes are interconnected by a dual concentric ring topology. Local controllers on any given node initiate bus operations on behalf of said processors and I/O adapters on that node. Snoop requests are launched onto the ring topology simultaneously in both directions. As the messages traverse the nodes on the ring, they trigger remote controllers to perform coherent actions such as cache accesses or directory updates. Messages arriving on each node from both directions are combined with each other and with locally generated responses to form cumulative final responses. Additionally, controllers on the requesting node may perform local coherent actions based on the information conveyed by the returning final responses.

US Patent:

7111130, Sep 19, 2006

Filed:

Apr 12, 2006

Appl. No.:

11/402599

Inventors:

Michael A. Blake - Wappingers Falls NY, US
Pak-kin Mak - Poughkeepsie NY, US
Adrian E. Seigler - Poughkeepsie NY, US
Gary A. VanHuben - Poughkeepsie NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/00

US Classification:

711147

Abstract:

A shared memory symmetrical processing system including a plurality of nodes each having a system control element for routing internodal communications. A first ring and a second ring interconnect the plurality of nodes, wherein data in said first ring flows in opposite directions with respect to said second ring. A receiver receives a plurality of incoming messages via the first or second ring and merges a plurality of incoming message responses with a local outgoing message response to provide a merged response. Each of the plurality of nodes includes any combination of the following: at least one processor, cache memory, a plurality of I/O adapters, and main memory. The system control element includes a plurality of controllers for maintaining coherency in the system.

US Patent:

8131937, Mar 6, 2012

Filed:

Jun 22, 2007

Appl. No.:

11/766977

Inventors:

Michael A. Blake - Wappingers Falls NY, US
Harmony L. Helterhoff - Austin TX, US
Arthur J. O'Neill - Wappingers Falls NY, US
Vesselina K. Papazova - Highland NY, US
Craig R. Walters - Highland NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 13/00

US Classification:

711133, 711E12055

Abstract:

Improved access to retained data useful to a system is accomplished by managing data flow through cache associated with the processor(s) of a multi-node system. A data management facility operable with the processors and memory array directs the flow of data from the processors to the memory array by determining the path along which data evicted from a level of cache close to one of the processors is to return to a main memory and directing evicted data to be stored, if possible, in a horizontally associated cache.

US Patent:

8364904, Jan 29, 2013

Filed:

Jun 21, 2010

Appl. No.:

12/819348

Inventors:

Michael A. Blake - Wappingers Falls NY, US
Lawrence D. Curley - Endwell NY, US
Garrett M. Drapala - Poughkeepsie NY, US
Edward J. Kaminski - Wynnewood PA, US
Craig R. Walters - Highland NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/00

US Classification:

711141

Abstract:

Horizontal cache persistence in a multi-compute node, SMP computer, including, responsive to a determination to evict a cache line on a first one of the compute nodes, broadcasting by a first compute node an eviction notice for the cache line; transmitting the state of the cache line receiving compute nodes, including, if the cache line is missing from a compute node, an indication whether that compute node has cache storage space available for the cache line; determining by the first compute node, according to the states of the cache line and space available, whether the first compute node can evict the cache line without writing the cache line to main memory; and updating by each compute node the state of the cache line in each compute node, in dependence upon one or more of the states of the cache line in all the compute nodes.

US Patent:

8381019, Feb 19, 2013

Filed:

Jun 24, 2010

Appl. No.:

12/822367

Inventors:

Michael A. Blake - Wappingers Falls NY, US
Timothy C. Bronson - Round Rock TX, US
Hieu T. Huynh - Pflugerville TX, US
Pak-kin Mak - Poughkeepsie NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 11/00

US Classification:

714 61, 714 611, 714 30, 714 42

Abstract:

Embedded dynamic random access memory (EDRAM) macro disablement in a cache memory includes isolating an EDRAM macro of a cache memory bank, the cache memory bank being divided into at least three rows of a plurality of EDRAM macros, the EDRAM macro being associated with one of the at least three rows, iteratively testing each line of the EDRAM macro, the testing including attempting at least one write operation at each line of the EDRAM macro, determining if an error occurred during the testing, and disabling write operations for an entire row of EDRAM macros associated with the EDRAM macro based on the determining.