Michael T Bye

US Patent:

7966591, Jun 21, 2011

Filed:

Oct 9, 2008

Appl. No.:

12/248765

Inventors:

John Thompson - Chippewa Falls WI, US
Michael Bye - Chippewa Falls WI, US

Assignee:

Cray, Inc. - Seattle WA

International Classification:

G06F 9/455
G06F 17/50

US Classification:

716106, 716100, 716101, 716103, 716104, 716107, 716110, 716111, 716112, 716116, 716117, 716118, 716136

Abstract:

Embodiments include a system and method for generating RTL description of an electronic device provided for a design test and a test bench environment to drive stimulus into the electronic device, identifying at least one register to be verified during the design test, authoring a property list including a plurality of properties, wherein each property includes a cause and an effect, creating a new property instance upon receiving an enqueue cause, transitioning a property instance from a waiting state to a pending state based on a dequeue cause, advancing property instances from the pending state to an active state and then to an expired state based on a defined time window, creating a current solution space including a plurality of solutions, wherein each of the plurality of solutions includes a list of unused active effects, inserting property instances into each of the plurality of solutions when the property instance enters to active state, pruning solutions from the current solutions space which have not used a property instance entering the expired state, and computing a new solution space based on the current solution space and target transition.

US Patent:

20100318741, Dec 16, 2010

Filed:

Jun 12, 2009

Appl. No.:

12/483915

Inventors:

Steven L. Scott - Chippewa Falls WI, US
Gregory J. Faanes - Chippewa Falls WI, US
Abdulla Bataineh - Eau Claire WI, US
Michael Bye - Chippewa Falls WI, US
Gerald A. Schwoerer - Chippewa Falls WI, US
Dennis C. Abts - Eleva WI, US

Assignee:

Cray Inc. - Seattle WA

International Classification:

G06F 12/08
G06F 12/00

US Classification:

711122, 711141, 711E12001, 711E12026

Abstract:

A multiprocessor computer system comprises a processing node having a plurality of processors and a local memory shared among processors in the node. An L data cache is local to each of the plurality of processors, and an L cache is local to each of the plurality of processors. An L cache is local the node but shared among the plurality of processors, and the L cache is a subset of data stored in the local memory. The L caches are subsets of the L cache, and the L caches are a subset of the L caches in the respective processors.

US Patent:

53922921, Feb 21, 1995

Filed:

Nov 10, 1993

Appl. No.:

8/149967

Inventors:

Thomas J. Davis - Chippewa Falls WI
Michael T. Bye - Chippewa Falls WI
Richard D. Pribnow - Chippewa Falls WI
Bricky A. Stephenson - Chippewa Falls WI

Assignee:

Cray Research, Inc. - Eagan MN

International Classification:

G06F 1120

US Classification:

371 111

Abstract:

A memory reconfiguration system dynamically configures spare chips into memory during system operation by shifting data around defective chips. The shifting of data around an entire memory chip allows the system to correct bit, addressing, and control errors or faults within the chip. When the system detects an error, or otherwise initiates a memory reconfiguration, it transmits a configuration code to shift registers for a memory write driver. The shift registers, in response to the configuration code, shift write data so that the data is effectively shifted around a particular memory chip and into a spare memory chip. The system selectively transmits the configuration code to shift registers for a memory read driver. Therefore, the system independently shifts data written to the memory inputs and data read from the memory outputs.

US Patent:

62566776, Jul 3, 2001

Filed:

Dec 16, 1997

Appl. No.:

8/991233

Inventors:

Richard D. Pribnow - Chippewa Falls WI
Michael T. Bye - Chippewa Falls WI
James G. Bravatto - Inver Grove Heights MN
John Theodore Kline - Apple Valley MN

Assignee:

Silicon Graphics, Inc. - Mountain View CA

International Classification:

G06F 1324

US Classification:

709250

Abstract:

A ring computer network system having a communication controller for controller the receipt and sending of packets or messages at each client computer. The interface associated with each client computer includes a send message buffer and a receive message buffer. The send message buffer has a send message buffer counter which increments upwardly in response to messages being received from the client computer for sending on the ring network. The communication controller sends messages from the send buffer until the send message buffer counter reaches the address or a value associated with the last received message. Similarly, the receive message buffer includes a receive message buffer counter which increments as each message is received to a receive message buffer counter value. The receive message buffer is emptied until the receive message buffer counter value is reached. The receive buffer can also have a foreground portion and a background portion.