Michael R Chester

US Patent:

57957975, Aug 18, 1998

Filed:

Aug 18, 1995

Appl. No.:

8/516709

Inventors:

Michael A. Chester - Thousand Oaks CA
Steven A. Michaelson - Moorpark CA

Assignee:

Teradyne, Inc. - Boston MA

International Classification:

H01L 2100
G11C 700
G11C 2900

US Classification:

438 4

Abstract:

A process for manufacturing semiconductor memories which includes a method of quickly and effectively identifying which faulty memory cells are to be replaced by redundant memory structures. Redundant rows and columns are assigned to replace rows and columns with faulty cells in an iterative process. At each pass, one row or column is identified for replacement. A row or column is selected for replacement based on priorities assigned to the faulty cells within the rows and columns. The highest priority cell for a row is the one in a column with the fewest other faulty cells. Where multiple cells have the same highest row priority, the cell in a row with the most faulty cells is given a higher priority. A similar dual measure is used for assigning column priorities to cells. Once a highest priority row and column are identified, the single element with the highest priority is identified.