Michael C Chisholm

US Patent:

60777834, Jun 20, 2000

Filed:

Jun 30, 1998

Appl. No.:

9/109335

Inventors:

Derryl D. J. Allman - Colorado Springs CO
David W. Daniel - Divide CO
Michael F. Chisholm - Garland TX

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H01L 21302

US Classification:

438691

Abstract:

A method of polishing a first layer of a semiconductor wafer down to a second layer of the semiconductor wafer is disclosed. One step of the method includes heating a back surface of the semiconductor wafer to a first temperature level so as to cause a front surface of the semiconductor wafer to have a second temperature level. Another step of the method includes polishing the semiconductor wafer whereby material of the first layer is removed from the semiconductor wafer. The polishing step causes the second temperature level of the front surface to change at a first rate as the material of the first layer is being removed. The method also includes the step of halting the polishing step in response to the second temperature level of the front surface changing at a second rate that is indicative of the second layer being polished during the polishing step. Polishing systems are also disclosed which detect a polishing endpoint for a semiconductor wafer based upon heat conducted through the semiconductor wafer.

US Patent:

62355902, May 22, 2001

Filed:

Dec 18, 1998

Appl. No.:

9/216394

Inventors:

David W. Daniel - Divide CO
Dianne G. Pinello - Woodland Park CO
Michael F. Chisholm - Garland TX

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H01L 218234

US Classification:

438275

Abstract:

Techniques for fabricating integrated circuits having devices with gate oxides having different thicknesses and a high nitrogen content include forming the gate oxides at pressures at least as high as 2. 0 atmospheres in an ambient of a nitrogen-containing gas. In one implementation, a substrate includes a first region for forming a first device having a gate oxide of a first thickness and a second region for forming a second device having a gate oxide of a second different thickness. A first oxynitride layer is formed on the first and second regions in an ambient comprising a nitrogen-containing gas at a pressure in a range of about 10 to about 15 atmospheres. A portion of the first oxynitride layer is removed to expose a surface of the substrate on the second region. Subsequently, a second oxynitride is formed over the first and second regions in an ambient comprising a nitrogen-containing gas at a pressure in a range of about 10 to about 15 atmospheres to form the first and second gate oxides. Respective gate electrodes are formed over the first and second gate oxides.

US Patent:

62682245, Jul 31, 2001

Filed:

Jun 30, 1998

Appl. No.:

9/108091

Inventors:

Gayle W. Miller - Colorado Springs CO
Michael F. Chisholm - Garland TX

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H01L 2100

US Classification:

438 10

Abstract:

A method of fabricating a semiconductor wafer having a polishing endpoint layer which is formed by implanting ions into the wafer includes the step of polishing the wafer in order to remove material from the wafer. The method also includes the step of detecting a first change in friction when material of the ion-implanted polishing endpoint layer begins to be removed during the polishing step. The method further includes the step of detecting a second change in friction when material of the ion-implanted polishing endpoint layer ceases to be removed during the polishing step. Moreover, the method includes the step of terminating the polishing step in response to detection of the second change in friction. An apparatus for polishing a semiconductor wafer down to an ion-implanted polishing endpoint layer in the wafer is also disclosed.