Alexander Kalnitsky - San Francisco CA, US Michael Church - Sebastian FL, US
Assignee:
Intersil Americas Inc. - Milpitas CA
International Classification:
G11C 16/04
US Classification:
3651851, 36518503
Abstract:
A multiple time programmable (MTP) memory cell, in accordance with an embodiment, includes a floating gate PMOS transistor, a high voltage NMOS transistor, and an n-well capacitor. The floating gate PMOS transistor includes a source that forms a first terminal of the memory cell, a drain and a gate. The high voltage NMOS transistor includes a source connected to ground, an extended drain connected to the drain of the PMOS transistor, and a gate forming a second terminal of the memory cell. The n-well capacitor includes a first terminal connected to the gate of the PMOS transistor, and a second terminal forming a third terminal of the memory cell. The floating gate PMOS transistor can store a logic state. Combinations of voltages can be applied to the first, second and third terminals of the memory cell to program, inhibit program, read and erase the logic state.
Multiple Time Programmable (Mtp) Pmos Floating Gate-Based Non-Volatile Memory Device For A General Purpose Cmos Technology With Thick Gate Oxide
Alexander Kalnitsky - San Francisco CA, US Michael D. Church - Sebastian FL, US
Assignee:
Intersil Americas Inc. - Milpitas CA
International Classification:
G11C 16/04
US Classification:
36518506, 365149
Abstract:
A multiple time programmable (MTP) memory cell, in accordance with an embodiment, includes a floating gate PMOS transistor, a high voltage NMOS transistor, and an n-well capacitor. The floating gate PMOS transistor includes a source that forms a first terminal of the memory cell, a drain and a gate. The high voltage NMOS transistor includes a source connected to ground, an extended drain connected to the drain of the PMOS transistor, and a gate forming a second terminal of the memory cell. The n-well capacitor includes a first terminal connected to the gate of the PMOS transistor, and a second terminal forming a third terminal of the memory cell. The floating gate PMOS transistor can store a logic state. Combinations of voltages can be applied to the first, second and third terminals of the memory cell to program, inhibit program, read and erase the logic state.
Multiple Time Programmable (Mtp) Pmos Floating Gate-Based Non-Volatile Memory Device For A General-Purpose Cmos Technology With Thick Gate Oxide
Alexander Kalnitsky - San Francisco CA, US Michael Church - Sebastian FL, US
Assignee:
Intersil Americas Inc. - Milpitas CA
International Classification:
G11C 16/04 G11C 11/34
US Classification:
36518518
Abstract:
A multiple time programmable (MTP) memory cell, in accordance with an embodiment, includes a floating gate PMOS transistor, a high voltage NMOS transistor, and an n-well capacitor. The floating gate PMOS transistor includes a source that forms a first terminal of the memory cell, a drain and a gate. The high voltage NMOS transistor includes a source connected to ground, an extended drain connected to the drain of the PMOS transistor, and a gate forming a second terminal of the memory cell. The n-well capacitor includes a first terminal connected to the gate of the PMOS transistor, and a second terminal forming a third terminal of the memory cell. The floating gate PMOS transistor can store a logic state. Combinations of voltages can be applied to the first, second and third terminals of the memory cell to program, inhibit program, read and erase the logic state.