Michael J Church

US Patent:

6350640, Feb 26, 2002

Filed:

Jul 18, 1994

Appl. No.:

08/276290

Inventors:

Robert T. Fuller - Melbourne Beach FL
Chris McCarty - Melbourne FL
John T. Gasner - Satellite Beach FL
Michael D. Church - Sebastian FL

Assignee:

Intersil Americas Inc. - Irvine CA

International Classification:

H01L 218238

US Classification:

438202, 438234

Abstract:

To program a CMOS memory, an auxiliary bipolar transistor is formed in a P-well adjacent to the P-well of an NMOS device of the CMOS memory, the auxiliary transistor being capable of forcing a large magnitude current through a fusible link, so as to program the electronic state of the CMOS memory cell into a prescribed binary (1/0) condition. A separate implant mask for the emitter region of the auxiliary transistor allows the geometry and impurity concentration profile of the emitter region to be tailored by a deep dual implant, so that the impurity concentration of the emitter region is not decreased, and yields a reduced base width for the auxiliary transistor to provide a relatively large current gain to blow the fuse, while allowing the doping parameters of the source/drain regions of the CMOS structure to be separately established to prevent thyristor latch-up.

US Patent:

6492225, Dec 10, 2002

Filed:

Dec 20, 2001

Appl. No.:

10/026346

Inventors:

Michael David Church - Sebastian FL

Assignee:

Intersil Americas Inc. - Irvine CA

International Classification:

H01L 218242

US Classification:

438241, 438258, 438297

Abstract:

An EPROM structure includes a NMOS transistor integrated with a capacitor. The terminal names of the NMOS transistor follow the conventional nomenclature: drain, source, body and gate. The gate of the NMOS transistor is connected directly and exclusively to one of the capacitor plates. In this configuration, the gate is now referred to as the âfloating gateâ. The remaining side of the capacitor is referred to as the âcontrol gateâ.

US Patent:

6566705, May 20, 2003

Filed:

Dec 20, 2001

Appl. No.:

10/026320

Inventors:

Michael David Church - Sebastian FL

Assignee:

Intersil Americas, Inc. - Irvine CA

International Classification:

H01L 2976

US Classification:

257314, 257315, 257318, 257327, 438201, 438211, 438257, 438263

Abstract:

An EPROM structure includes a NMOS transistor integrated with a capacitor. The terminal names of the NMOS transistor follow the conventional nomenclature: drain, source, body and gate. The gate of the NMOS transistor is connected directly and exclusively to one of the capacitor plates. In this configuration, the gate is now referred to as the âfloating gateâ. The remaining side of the capacitor is referred to as the âcontrol gateâ.

US Patent:

6621116, Sep 16, 2003

Filed:

Dec 20, 2001

Appl. No.:

10/026345

Inventors:

Michael David Church - Sebastian FL 32958

International Classification:

H01L 2976

US Classification:

257314, 257315, 257376, 257392, 257402, 257487, 257327, 257336, 257344, 257394, 257404, 257408, 438217, 438276, 438289

Abstract:

An EPROM structure includes a NMOS transistor integrated with a capacitor. The terminal names of the NMOS transistor follow the conventional nomenclature: drain, source, body and gate. The gate of the NMOS transistor is connected directly and exclusively to one of the capacitor plates. In this configuration, the gate is now referred to as the âfloating gateâ. The remaining side of the capacitor is referred to as the âcontrol gateâ.

US Patent:

6798024, Sep 28, 2004

Filed:

Jun 29, 2000

Appl. No.:

09/607080

Inventors:

Donald Hemmenway - Melbourne FL
Jose Delgado - Valkaria FL
John Butler - Palm Bay FL
Anthony Rivoli - Palm Bay FL
Michael D. Church - Sebastian FL
George V. Rouse - Indialantic FL
Lawrence G. Pearce - Palm Bay FL
George S. Bajor - Melbourne FL

Assignee:

Intersil Americas Inc. - Milpitas CA

International Classification:

H01L 2976

US Classification:

257370

Abstract:

A low temperature coefficient resistor (TCRL) has some unrepaired ion implant damage. The damaged portion raises the resistance and renders the resistor less sensitive to operating temperature fluctuations A polysilicon thin film low temperature coefficient resistor and a method for the resistors fabrication overcomes the coefficient of resistance problem of the prior art, while at the same time eliminating steps from the BiCMOS fabrication process, optimizing bipolar design tradeoffs, and improving passive device isolation. A low temperature coefficient of resistance resistor (TCRL) is formed on a layer of insulation, typically silicon dioxide or silicon nitride, the layer comprising polysilicon having a relatively high concentration of dopants of one or more species. An annealing process is used for the implanted resistor which is shorter than that for typical prior art implanted resistors, leaving some intentional unannealed damage in the resistor. The planned damage gives the TCRL a higher resistance without increasing its temperature coefficient.

US Patent:

6812108, Nov 2, 2004

Filed:

Mar 19, 2003

Appl. No.:

10/393181

Inventors:

Donald Hemmenway - Melbourne FL
Jose Delgado - Valkaria FL
John Butler - Palm Bay FL
Anthony Rivoli - Palm Bay FL
Michael D. Church - Sebastian FL
George V. Rouse - Indialantic FL
Lawrence G. Pearce - Palm Bay FL
George Bajor - Melbourne FL

Assignee:

Intersil Corporation - Palm Bay FL

International Classification:

H01L 2120

US Classification:

438385, 438330, 438382

Abstract:

A low temperature coefficient resistor(TCRL) has some unrepaired ion implant damage. The damaged portion raises the resistance and renders the resistor less sensitive to operating temperature fluctuations. A polysilicon thin film low temperature coefficient resistor and a method for the resistors fabrication overcomes the coefficient of resistance problem of the prior art, while at the same time eliminating steps from the BiCMOS fabrication process, optimizing bipolar design tradeoffs, and improving passive device isolation. A low temperature coefficient of resistance resistor (TCRL) is formed on a layer of insulation, typically silicon dioxide or silicon nitride, the layer comprising polysilicon having a relatively high concentration of dopants of one or more species. An annealing process is used for the implanted resistor which is shorter than that for typical prior art implanted resistors, leaving some intentional unannealed damage in the resistor. The planned damage gives the TCRL a higher resistance without increasing its temperature coefficient.

US Patent:

6921690, Jul 26, 2005

Filed:

Dec 20, 2001

Appl. No.:

10/026294

Inventors:

Michael David Church - Sebastian FL, US

Assignee:

Intersil Americas Inc. - Irvine CA

International Classification:

H01L021/8242

US Classification:

438241, 438258, 438297

Abstract:

An EPROM structure includes a NMOS transistor integrated with a capacitor. The terminal names of the NMOS transistor follow the conventional nomenclature: drain, source, body and gate. The gate of the NMOS transistor is connected directly and exclusively to one of the capacitor plates. In this configuration, the gate is now referred to as the “floating gate”. The remaining side of the capacitor is referred to as the “control gate”.

US Patent:

7005369, Feb 28, 2006

Filed:

Oct 31, 2003

Appl. No.:

10/698184

Inventors:

John T. Gasner - Satellite Beach FL, US
Michael D. Church - Sebastian FL, US
Sameer D. Parab - Fremont CA, US
David A. Decrosta - Melbourne FL, US
Robert L. Lomenick - Palm Bay FL, US
Chris A. McCarty - Melbourne FL, US

Assignee:

Intersil American Inc. - Milpitas CA

International Classification:

H01L 21/44

US Classification:

438614, 438618, 438622, 438624, 438625, 438652

Abstract:

An integrated circuit with circuits under a bond pad. In one embodiment, the integrated circuit comprises a substrate, a top conductive layer, one or more intermediate conductive layers, layers of insulating material and devices. The top conductive layer has a at least one bonding pad and a sub-layer of relatively stiff material. The one or more intermediate conductive layers are formed between the top conductive layer and the substrate. The layers of insulating material separate the conductive layers. Moreover, one layer of the layers of insulating material is relatively hard and is located between the top conductive layer and an intermediate conductive layer closest to the top conductive layer. The devices are formed in the integrated circuit. In addition, at least the intermediate conductive layer closest to the top conductive layer is adapted for functional interconnections of select devices under the bond pad.