Michael J Clinton

US Patent:

8437214, May 7, 2013

Filed:

Jul 17, 2012

Appl. No.:

13/551057

Inventors:

Donald Mikan - Austin TX, US
Hugh Mair - Fairview TX, US
Theodore W. Houston - Richardson TX, US
Michael Patrick Clinton - Allen TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G11C 5/14

US Classification:

365227, 36518915, 36518916, 365154, 365228

Abstract:

A memory array has a memory cell that comprises a storage element storing a logical state at a reduced voltage during at least one functional operation and a write access circuit configured to connect the storage element to at least a first write bit line in response to a write signal on the write word line for writing the logical state to the memory cell. The memory cell further comprises a read access circuit including an input node connected to the storage element and an output node connected to a read bit line of the memory array. The read access circuit is enabled and configured to read the logic state of the storage element in response to a read signal on the read word line. The reduced voltage is reduced relative to an operating voltage of at least one peripheral circuit associated with reading and/or writing of the memory cell.

US Patent:

20220328082, Oct 13, 2022

Filed:

Jun 24, 2022

Appl. No.:

17/848599

Inventors:

- Hsinchu, TW
Michael Clinton - Austin TX, US

International Classification:

G11C 7/22
G11C 11/419
G11C 7/08
G11C 5/14
G11C 8/08
H01L 27/11
G11C 7/12

Abstract:

Systems, devices, and methods are provided for enabling turbo mode for static random access memory (SRAM) devices. A cell circuit is coupled between a bit line pair and configured to perform read or write operations of a memory device. A sense amplifier circuit is coupled between the bit line pair and configured to sense a voltage differential between the bit line pair. A tracking circuit includes a tracking bit line (DBL) and is configured to monitor operation of the cell circuit and send a sense amplifier enable signal to the sense amplifier at a predetermined frequency rate based on a voltage level of the DBL. A turbo circuit is coupled to a turbo signal and configured to modify the voltage of the tracking bit line enabling sending of the sense amplifier enable signal at a rate faster than the predetermined frequency rate.

US Patent:

20190096477, Mar 28, 2019

Filed:

Sep 24, 2018

Appl. No.:

16/139779

Inventors:

- Hsinchu, TW
Michael Clinton - Austin TX, US

International Classification:

G11C 11/419
G11C 7/08
G11C 7/12
G11C 8/08
H01L 27/11
G11C 5/14

Abstract:

Systems, devices, and methods are provided for enabling turbo mode for static random access memory (SRAM) devices. A cell circuit is coupled between a bit line pair and configured to perform read or write operations of a memory device. A sense amplifier circuit is coupled between the bit line pair and configured to sense a voltage differential between the bit line pair. A tracking circuit includes a tracking bit line (DBL) and is configured to monitor operation of the cell circuit and send a sense amplifier enable signal to the sense amplifier at a predetermined frequency rate based on a voltage level of the DBL. A turbo circuit is coupled to a turbo signal and configured to modify the voltage of the tracking bit line enabling sending of the sense amplifier enable signal at a rate faster than the predetermined frequency rate.

US Patent:

20170243620, Aug 24, 2017

Filed:

May 8, 2017

Appl. No.:

15/589313

Inventors:

- HSINCHU, TW
CHITING CHENG - TAICHUNG CITY, TW
CHENG HUNG LEE - HSINCHU, TW
HUNG-JEN LIAO - HSIN-CHU CITY, TW
MICHAEL CLINTON - AUSTIN TX, US

International Classification:

G11C 7/12
G11C 8/06
G11C 7/22
G11C 5/14
G11C 7/10
G11C 7/06
G11C 8/10
G11C 8/08

Abstract:

A dual rail memory operable at a first voltage and a second voltage, the dual rail memory includes: a memory array operates at the first voltage; a word line driver circuit configured to drive a word line of the memory array to the first voltage; a data path configured to transmit an input data signal or an output data signal; and a control circuit configured to generate control signals to the memory array, the word line driver circuit and the data path; wherein the data path and the control circuit are configured to operate at both the first and second voltages. Associated memory macro and method are also disclosed.

US Patent:

20170084317, Mar 23, 2017

Filed:

Oct 27, 2015

Appl. No.:

14/924069

Inventors:

- HSINCHU, TW
CHITING CHENG - TAICHUNG CITY, TW
CHENG HUNG LEE - HSINCHU, TW
HUNG-JEN LIAO - HSIN-CHU CITY, TW
MICHAEL CLINTON - AUSTIN TX, US

International Classification:

G11C 7/12
G11C 7/10
G11C 8/08
G11C 7/22
G11C 8/10
G11C 8/06
G11C 5/14
G11C 7/06

Abstract:

A dual rail memory operable at a first voltage and a second voltage, the dual rail memory includes: a memory array operates at the first voltage; a word line driver circuit configured to drive a word line of the memory array to the first voltage; a data path configured to transmit an input data signal or an output data signal; and a control circuit configured to generate control signals to the memory array, the word line driver circuit and the data path; wherein the data path and the control circuit are configured to operate at both the first and second voltages. Associated memory macro and method are also disclosed.

US Patent:

20140241083, Aug 28, 2014

Filed:

May 7, 2014

Appl. No.:

14/271810

Inventors:

- Dallas TX, US
Vinod J. Menezes - Bangalore, IN
Theodore W. Houston - Richardson TX, US
Michael Patrick Clinton - Austin TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G11C 7/02
G11C 8/08
G11C 11/419

US Classification:

365194, 365206

Abstract:

A memory circuit includes a bit cell that receives a word line, complementary bit lines and an array supply voltage; a word line driver coupled to the word line, the word line driver receiving one of the array supply voltage and a periphery supply voltage; and a word line suppression circuit coupled to the word line. The word line suppression circuit includes a diode and a switch coupled in series. The switch is responsive to the array supply voltage. The word line suppression circuit limits a word line voltage to a value lower than the array supply voltage such that the static noise margin (SNM) of the bit cell is increased.

US Patent:

20140241089, Aug 28, 2014

Filed:

May 7, 2014

Appl. No.:

14/271765

Inventors:

- Dallas TX, US
Vinod J. Menezes - Bangalore, IN
Theodore W. Houston - Richardson TX, US
Michael Patrick Clinton - Austin TX, US

Assignee:

TEXAS INSTRUMENTS INCORPORATED - Dallas TX

International Classification:

G11C 7/02
G11C 11/419
G11C 8/08

US Classification:

365206

Abstract:

A memory circuit includes a bit cell that receives a word line, complementary bit lines and an array supply voltage; a word line driver coupled to the word line, the word line driver receiving one of the array supply voltage and a periphery supply voltage; and a word line suppression circuit coupled to the word line. The word line suppression circuit includes a diode and a switch coupled in series. The switch is responsive to the array supply voltage. The word line suppression circuit limits a word line voltage to a value lower than the array supply voltage such that the static noise margin (SNM) of the bit cell is increased.

US Patent:

20140140121, May 22, 2014

Filed:

Jun 27, 2013

Appl. No.:

13/929121

Inventors:

- Dallas TX, US
Michael Patrick Clinton - Austin TX, US

International Classification:

G11C 17/08

US Classification:

365104, 365103

Abstract:

A two-bit read-only-memory (ROM) cell and method of sensing its data state. Each ROM cell in an array includes a single n-channel metal-oxide-semiconductor (MOS) transistor with a source biased to a reference voltage, and its drain connected by a contact or via to one or none of first, second, and third bit lines associated with its column in the array. Each row in the array is associated with a word line serving as the transistor gates for the cells in that row. In response to a column address, a column select circuit selects one pair of the three bit lines to be applied to a sense line in wired-NOR fashion for sensing.