Michael V Cordoba

US Patent:

6952116, Oct 4, 2005

Filed:

Sep 29, 2003

Appl. No.:

10/675661

Inventors:

Michael V. Cordoba - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H03K019/094
G05F003/02

US Classification:

326 88, 327536, 36518911

Abstract:

A charge pump includes a pair of capacitors each having a first terminal coupled to a pumped node. A charge voltage is initially applied to the pumped node to charge the capacitors. A second terminal of the first capacitor is then pumped to increase the voltage at the pumped node, with the charge of the first capacitor being shared with the second capacitor. The second terminal of the second capacitor is then pumped to again increase the voltage at the pumped node. The pumped node is then coupled to an output terminal.

US Patent:

7006389, Feb 28, 2006

Filed:

Dec 12, 2003

Appl. No.:

10/734944

Inventors:

Michael V. Cordoba - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 7/00
H03K 19/0175

US Classification:

36518909, 36518911, 326 63, 326 68, 326 81, 327333

Abstract:

A method and apparatus is provided for a voltage translator for performing a voltage-level translation of a signal. The voltage translator of the present invention includes a first transistor that is coupled to a control signal. The control signal is in a first voltage range. The voltage translator also includes a first one-shot circuit driven by the first transistor. The first one-shot circuit is capable of providing a pulse. The voltage translator also includes a second transistor capable of receiving a complementary signal of the control signal. A first pair and a second pair of transistors are included in the voltage translator. Each pair of transistors is operatively coupled to the first and second transistors. The first and second pairs of transistors are adapted to provide a transition of a signal from a first voltage range to a second voltage range.

US Patent:

7071730, Jul 4, 2006

Filed:

Jun 9, 2004

Appl. No.:

10/865725

Inventors:

Michael V Cordoba - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H03K 19/094

US Classification:

326 38

Abstract:

Circuitry and methods for implementing voltage level translators at relatively low source voltages are provided. The circuitry and methods utilize voltage protection circuitry to ensure that voltages in the circuitry do not exceed predetermined thresholds that, if exceeded, would cause malfunction. In one embodiment of the invention, voltage level translation circuitry is provided to boost voltage from a source voltage (e. g. , V) to a voltage that is higher in potential (e. g. , V) than the source voltage. In another embodiment of the invention, voltage level translation circuitry is provided to pull a ground voltage down to a potential (e. g. , V) that is lower in voltage than the ground voltage.

US Patent:

7200053, Apr 3, 2007

Filed:

Sep 1, 2004

Appl. No.:

10/931587

Inventors:

Tae H. Kim - Boise ID, US
Michael V. Cordoba - Boise ID, US
Howard C. Kirsch - Eagle ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 7/00

US Classification:

36518911, 365203

Abstract:

A voltage level translator boosts the gate voltage of a transistor, and increases the gate to source voltage, to allow operation over a wider range of supply voltages. The P/N ratio of transistors in the voltage level translator is therefore increased, and control of the flipping of nodes is dependent on gate voltages as opposed to P/N ratios.

US Patent:

7227793, Jun 5, 2007

Filed:

Dec 8, 2005

Appl. No.:

11/297624

Inventors:

Michael V. Cordoba - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 7/00
H03K 19/0175

US Classification:

36518909, 36518911, 326 63, 326 68, 326 81, 327333

Abstract:

A method and apparatus is provided for a voltage translator for performing a voltage-level translation of a signal. The voltage translator of the present invention includes a first transistor that is coupled to a control signal. The control signal is in a first voltage range. The voltage translator also includes a first one-shot circuit driven by the first transistor. The first one-shot circuit is capable of providing a pulse. The voltage translator also includes a second transistor capable of receiving a complementary signal of the control signal. A first pair and a second pair of transistors are included in the voltage translator. Each pair of transistors is operatively coupled to the first and second transistors. The first and second pairs of transistors are adapted to provide a transition of a signal from a first voltage range to a second voltage range.

US Patent:

7375554, May 20, 2008

Filed:

May 24, 2006

Appl. No.:

11/440250

Inventors:

Michael V Cordoba - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H03K 19/094

US Classification:

326 68

Abstract:

Circuitry and methods for implementing voltage level translators at relatively low source voltages are provided. The circuitry and methods utilize voltage protection circuitry to ensure that voltages in the circuitry do not exceed predetermined thresholds that, if exceeded, would cause malfunction. In one embodiment of the invention, voltage level translation circuitry is provided to boost voltage from a source voltage (e. g. , V) to a voltage that is higher in potential (e. g. , V) than the source voltage. In another embodiment of the invention, voltage level translation circuitry is provided to pull a ground voltage down to a potential (e. g. , V) that is lower in voltage than the ground voltage.

US Patent:

7382177, Jun 3, 2008

Filed:

Oct 25, 2004

Appl. No.:

10/972544

Inventors:

Michael Cordoba - Boise ID, US
Hal Butler - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G05F 3/02

US Classification:

327536, 363 60

Abstract:

A voltage pump comprising a charging transistor responsive to a first control signal, the charging transistor operable to connect a node to a first voltage, a pumping capacitor responsive to a second control signal, the pumping capacitor operable to pump additional charge the node, and a pumping transistor responsive to a third control signal, the pumping transistor operable to connect the node to an output, wherein the charging transistor, the pumping capacitor, and the pumping transistor are thin-gate transistors. A method comprising charging a node to a first voltage, boosting the node to a second voltage, and connecting the node to an output, wherein the absolute value of the gate-to-source, gate-to-drain, and drain-to-source voltages of the plurality of thin-gate transistors does not exceed the absolute value of a supply voltage. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

US Patent:

7440344, Oct 21, 2008

Filed:

Apr 3, 2007

Appl. No.:

11/732219

Inventors:

Tae H. Kim - Boise ID, US
Michael V. Cordoba - Boise ID, US
Howard C. Kirsch - Eagle ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 7/00

US Classification:

36518911, 36518906, 365203

Abstract:

A voltage level translator boosts the gate voltage of a transistor, and increases the gate to source voltage, to allow operation over a wider range of supply voltages. The P/N ratio of transistors in the voltage level translator is therefore increased, and control of the flipping of nodes is dependent on gate voltages as opposed to P/N ratios.