Michael J Corrigan

US Patent:

6574721, Jun 3, 2003

Filed:

Aug 31, 1999

Appl. No.:

09/387343

Inventors:

Patrick James Christenson - Lake City MN
Brian Eldridge Clark - Rochester MN
Michael J. Corrigan - Rochester MN
Paul LuVerne Godtland - Rochester MN
Richard Karl Kirkman - Rochester MN
Donald Arthur Morrison - Rochester MN
Scott Alan Plaetzer - Rochester MN

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1206

US Classification:

711209, 711203, 711112, 711163, 711206

Abstract:

An apparatus and method provide simultaneous local and global addressing capabilities in a computer system. A global address space is defined that may be accessed by all processes. In addition, each process has a local address space that is local (and therefore available) only to that process. An address space processor is implemented in software to perform system functions that distinguish between local addresses and global addresses. In the preferred embodiments, the local address space has a size that is a multiple of the size of a segment of global address space. When the hardware indicates a page fault, the address space processor determines whether the address being translated is a local address or a global address. If the address is a local address, the address space processor uses a local directory to process the page fault. If the address is a global address, the address space processor uses a global directory to process the page fault.

US Patent:

6691146, Feb 10, 2004

Filed:

May 19, 1999

Appl. No.:

09/314214

Inventors:

Troy David Armstrong - Rochester MN
William Joseph Armstrong - Kasson MN
Michael Joseph Corrigan - Rochester MN
Naresh Nayar - Rochester MN
Thomas Rembert Sand - Rochester MN
Jeffrey Jay Scheel - Rochester MN
Erik Tkal - Rochester MN
Kenneth Charles Vossen - Kasson MN

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 900

US Classification:

709100, 709329, 709224

Abstract:

A partition manager for managing logical partitions in a computer system includes hooks to low-level operating system code in one of the logical partitions. By using the operating system code to manage the resources of a computer system, any changes that are made to the operating system are automatically reflected in the function of the partition manager. In addition, low-level functions of operating systems, which are often well-debugged and tested, can be used when generating a new partition manager, greatly simplifying the time and reducing the cost of producing a partition manager.

US Patent:

6772259, Aug 3, 2004

Filed:

Sep 12, 2001

Appl. No.:

09/952852

Inventors:

Michael Joseph Corrigan - Rochester MN
David Robert Engebretsen - Cannon Falls MN

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1324

US Classification:

710260, 712 13

Abstract:

According to the present invention, when an interrupt occurs in a computer system running an operating system, control takes a separate code path in the operating system, depending on whether the computer system is in non-partitioned mode or partitioned mode, before converging to a common mode-independent interrupt handler that services the interrupt. Along each separate code path, hardware state of the computer system which is relevant to the processing of the interrupt is changed to a consistent hardware state so that the common mode-independent interrupt handler can run properly in both modes.

US Patent:

6990560, Jan 24, 2006

Filed:

Jan 16, 2003

Appl. No.:

10/346010

Inventors:

William Joseph Armstrong - Rochester MN, US
Michael Joseph Corrigan - Rochester MN, US
Gary Ross Ricard - Chatfield MN, US
Timothy Joseph Torzewski - Rochester MN, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/02

US Classification:

711152

Abstract:

A task synchronization mechanism operates on a global lock that is shared between processors an on local locks that are not shared between processors. The local locks are processor-specific locks. Each processor-specific lock is dedicated to a particular processor in the system. When shared access to a resource is required, a processor updates its processor-specific lock to indicate the processor is sharing the resource. Because each processor-specific lock is dedicated to a particular processor, this eliminates a significant portion of the memory bus traffic associated with all processors reading and updating the same lock. When exclusive access to a resource is required, the requesting processor waits until the count of all processor-specific locks indicate that none of these processors have a lock on the resource. Once no processor has a lock on the resource, exclusive access to the resource may be granted.

US Patent:

7296120, Nov 13, 2007

Filed:

Nov 18, 2004

Appl. No.:

10/992436

Inventors:

Michael Joseph Corrigan - Rochester MN, US
Timothy Joseph Torzewski - Rochester MN, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/00

US Classification:

711144, 711156, 703 26, 703 27, 712 22, 712 24

Abstract:

Disclosed is an apparatus, method, and program product that provides atomic, multi-word load support without incurring additional memory utilization. A double-word is atomically loaded without the use of one or more additional fields and without a lock. An invalidity marker is used in connection with a cache miss time to ascertain whether a loaded double-word has been stored and loaded atomically, and is thus, valid.

US Patent:

7389400, Jun 17, 2008

Filed:

Dec 15, 2005

Appl. No.:

11/304136

Inventors:

Michael J. Corrigan - Rochester MN, US
Paul LuVerne Godtland - Rochester MN, US
Joaquin Hinojosa - Round Rock TX, US
Cathy May - Millwood NY, US
Naresh Nayar - Rochester MN, US
Edward John Silha - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/00

US Classification:

711203, 711100, 711133, 711154, 711205, 711206, 711207

Abstract:

An apparatus and method selectively invalidate entries in an address translation cache instead of invalidating all, or nearly all, entries. One or more translation mode bits are provided in each entry in the address translation cache. These translation mode bits may be set according to the addressing mode used to create the cache entry. One or more “hint bits” are defined in an instruction that allow specifying which of the entries in the address translation cache are selectively preserved during an invalidation operation according to the value(s) of the translation mode bit(s). In the alternative, multiple instructions may be defined to preserve entries in the address translation cache that have specified addressing modes. In this manner, more intelligence is used to recognize that some entries in the address translation cache may be valid after a task or partition switch, and may therefore be retained, while other entries in the address translation cache are invalidated.

US Patent:

7512826, Mar 31, 2009

Filed:

Apr 20, 2005

Appl. No.:

11/110180

Inventors:

William Joseph Armstrong - Rochester MN, US
Michael J. Corrigan - Rochester MN, US
Naresh Nayar - Rochester MN, US
Scott Barnett Swaney - Catskill NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1/12

US Classification:

713375, 713400

Abstract:

A method, apparatus, and computer program product are disclosed in a data processing system for providing a virtualized time base in a logically partitioned data processing system. A time base is determined for each one of multiple processor cores. The time base is used to indicate a current time to one of the processor cores for which the time base is determined. The time bases are synchronized together for the processor cores such that each one of the processor cores includes its own copy of a synchronized time base. For one of the processor cores, a virtualized time base is generated that is different from the synchronized time base but that remains synchronized with at least a portion of the synchronized time base. The processor core utilizes the virtualized time base instead of the synchronized time base for indicating the current time to the processor core. The synchronized time bases and the portion of the virtualized time base remaining in synchronization together.

US Patent:

7802252, Sep 21, 2010

Filed:

Jan 9, 2007

Appl. No.:

11/621393

Inventors:

William J. Armstrong - Rochester MN, US
Richard L. Arndt - Austin TX, US
Michael J. Corrigan - Rochester MN, US
Giles R. Frazier - Austin TX, US
Timothy R. Marchini - Hyde Park NY, US
Cathy May - Millwood NY, US
Naresh Nayar - Rochester MN, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9/46
G06F 9/50

US Classification:

718 1, 718104, 718107, 712 1, 712 43, 712229

Abstract:

A method and system for selecting the architecture level to which a processor appears to conform within a computing environment when executing specific logical partitions or programs and performing migration among different levels of processor architecture. The method utilizes a “processor compatibility register” (PCR) that controls the level of the architecture that the processor appears to support. In one embodiment, the PCR is accessible only to super-privileged software. The super-privileged software sets bits in the PCR that specify the architecture level that the processor is to appear to support so that when the program runs on the processor, the processor behaves in accordance with the architecture level for which the program was designed.